SIMD Processor Cycle Compression for Divergent Execution
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Solution Overview
Problem
SIMD control flow divergence leads to performance losses due to diminished SIMD efficiency, particularly in processors with execution units having fewer data paths than the width of SIMD instructions, resulting in increased execution cycles and reduced throughput.
Innovation Solution
Implementing cycle compression techniques such as Basic Cycle Compression (BCC) and Swizzled Cycle Compression (SCC) to identify and remove unused execution cycles by analyzing channel enable masks and rearranging channel positions, allowing for the harvesting of execution cycles and improving SIMD efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential execution of all control flow paths is used to address branch divergence hazard, then control flow divergence is handled, but execute time increases and compute throughput decreases
Solution Approach 1:
The execution cycles are segmented into used and unused portions based on channel enable masks. The processor identifies which data paths are active and which are inactive, then segments the execution cycles accordingly, allowing unused cycles to be removed and used cycles to be executed sequentially.
Solution Approach 2:
Unused execution cycles are extracted and removed from the execution sequence. By analyzing channel enable masks, the processor identifies cycles where all data paths are inactive and extracts these unused cycles from the execution timeline, reducing total execution time.
2Productivity
If SIMD control flow remains synchronized across all data paths, then execution efficiency is high, but control flow flexibility is reduced
Solution Approach 1:
The execution model transitions from static synchronized execution to dynamic execution where cycle compression is applied adaptively based on runtime channel enable masks. The processor dynamically identifies and compresses unused cycles while maintaining synchronized execution for active data paths, achieving both efficiency and flexibility.
Solution Approach 2:
The execution parameters are changed by varying the number of execution cycles based on channel enable masks. When divergence is detected, the processor changes the execution parameter from fixed synchronized cycles to variable compressed cycles, allowing active data paths to execute efficiently while inactive paths are skipped.
3Adaptability or versatility
If nested control flow is used to implement complex logic, then functionality is enhanced, but SIMD efficiency and compute throughput are reduced
Solution Approach 1:
Unused execution cycles within nested control flow structures are extracted and removed. The processor analyzes channel enable masks at each level of nested control flow, identifying unused cycles even in complex nested scenarios, and extracts them to maintain high compute throughput while preserving full control flow capability.
Data Source
AI summary
In one embodiment, the present invention includes a processor with a vector execution unit to execute a vector instruction on a vector having a plurality of individual data elements, where the vector instruction is of a first width and the vector execution unit is of a smaller width. The processor further includes a control logic coupled to the vector execution unit to compress a number of execution cycles consumed in execution of the vector instruction when at least some of the individual data elements are not to be operated on by the vector instruction. Other embodiments are described and claimed.