Reduced Precision SIMD Dataflow Architecture for ML Efficiency
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Solution Overview
Problem
Current SIMD and SIMT architectures face inefficiencies due to high instruction overheads and shared register-file communication overheads, which hinder performance and power efficiency in machine learning and deep learning applications, especially when optimized for reduced precision execution units.
Innovation Solution
A reduced precision based programmable SIMD-DF architecture that minimizes instruction overheads and eliminates shared register-files by using independent execution units with private register files and FIFO data exchange, allowing for parallel operation of multiple execution units within each element to reduce area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If shared register-files are used in SIMD architectures, then instruction overhead is reduced, but communication overhead between execution units increases
Solution Approach 1:
The patent divides the monolithic shared register file into multiple independent private register files, one for each execution unit. This segmentation eliminates the need for complex sharing mechanisms and reduces communication overhead while maintaining data accessibility through the dataflow graph structure.
Solution Approach 2:
The patent introduces a dataflow graph as an intermediary structure that mediates data exchange between execution units with private register files. This graph-based intermediary enables efficient data sharing without requiring direct access to shared register files, thus reducing communication overhead.
2Productivity
If multiple execution units operate in parallel within each element, then productivity increases, but area consumption increases
Solution Approach 1:
The patent merges multiple execution units into single execution elements, where each element contains several execution units that can operate in parallel. This merging allows shared resources within each element, reducing overall area consumption while maintaining high parallel processing capability across the array of elements.
Solution Approach 2:
The patent organizes execution units in a two-dimensional array of execution elements, transitioning from a flat single-element design to a structured multi-element architecture. This dimensional organization enables parallel operation across elements while sharing resources within each element, optimizing both productivity and area utilization.
3Use of energy by stationary object
If reduced precision execution units are used, then power consumption decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements different precision levels for different execution units within the same array, allowing each unit to be optimized for its specific computational requirements. This local quality approach enables reduced precision units for power-sensitive operations while maintaining higher precision where needed, balancing power consumption and manufacturing precision requirements.
Data Source
AI summary
A reduced precision based programmable and single instruction multiple data (SIMD) dataflow architecture includes reduced precision execution units with a majority of the execution units operating at reduced precision and a minority of the execution units are capable of operating at higher precision. The execution units operate in parallel within a programmable execution element to share instruction fetch, decode, and issue pipelines and operate on the same instruction in lock-step to minimize instruction-related overhead.