SIMD DSP Circuit with Parallel Adders for PLD Bottlenecks
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Solution Overview
Problem
The increasing demand for real-time, concurrent arithmetic operations in digital signal processing (DSP) applications, particularly in 3G base stations, is not adequately met by traditional DSP chips or Programmable Logic Devices (PLDs) due to bottlenecks in the PLD fabric, necessitating a more efficient digital signal processing circuit design.
Innovation Solution
A digital signal processing circuit with a single-instruction-multiple-data (SIMD) architecture, featuring multiplexers controlled by opcodes, an arithmetic logic unit with adders, and a carry lookahead adder, allowing concurrent operations and improved performance by replacing multiple DSP elements with application-specific circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple DSP elements are configured in PLD to allow concurrent DSP operations, then the number of arithmetic operations per second is improved, but the fabric of the PLD becomes a bottleneck
Solution Approach 1:
The PLD is segmented into multiple dedicated DSP slices, each containing specialized hardware components (multipliers, adders, accumulators) configured for specific DSP operations. This segmentation allows concurrent operations in each slice while reducing the burden on the general-purpose fabric interconnect structure.
Solution Approach 2:
A dedicated interconnect structure acts as an intermediary between DSP slices, providing specialized data pathways that reduce the load on the main PLD fabric. This intermediary interconnect is optimized specifically for DSP data flow patterns, enabling high-speed concurrent operations without overwhelming the general fabric.
2Productivity
If traditional DSP chips are used, then the device structure is simple, but the demand for real-time concurrent arithmetic operations is not adequately met
Solution Approach 1:
Multiple DSP functional elements (multipliers, adders, accumulators, registers) are merged into integrated DSP slices that can operate concurrently. Each slice combines these elements in a unified structure, enabling multiple arithmetic operations to proceed in parallel while maintaining a systematic overall architecture.
Solution Approach 2:
The DSP slices incorporate programmable control logic and configurable data paths that allow dynamic reconfiguration for different DSP algorithms. This dynamic capability enables the same hardware structure to adapt to various real-time processing requirements without sacrificing performance.
Data Source
AI summary
An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.