Reconfigurable SIMD Engine with Rewritable Control Memory
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Solution Overview
Problem
Current SIMD computing systems lack flexibility and efficiency in performing custom operations due to fixed instruction sets, which limits their ability to adapt to changing application requirements and increases hardware downtime during system upgrades.
Innovation Solution
A SIMD computing system with a rewritable control memory that allows control signals to configure SIMD processing elements to perform selected operations, enabling customizable and reconfigurable SIMD operations based on decoded instructions, and utilizing a pipelined processor with a decode stage to manage control signals for multiple SIMD processing elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fixed instruction sets are used in SIMD computing systems, then hardware structure is simplified and manufacturing is easier, but system flexibility and adaptability to changing application requirements deteriorate
Solution Approach 1:
The patent implements a reconfigurable SIMD engine where the control memory can be dynamically rewritten to change SIMD operations at runtime. The control signals stored in control memory locations can be modified to define custom SIMD operations, allowing the system to adapt to different application requirements without hardware changes. This dynamic reconfiguration capability resolves the contradiction by maintaining simple hardware structure while enabling high adaptability through software-controlled flexibility.
2Adaptability or versatility
If custom SIMD operations are implemented through hardware modifications, then operation customization capability is improved, but hardware downtime during system upgrades increases
Solution Approach 1:
The patent uses a control memory structure that stores control signals defining SIMD operations. Instead of modifying hardware, the system copies operation definitions into the control memory, which can be rewritten without halting the processor. The decode stage retrieves control signals from control memory locations based on decoded instructions, allowing custom operations to be implemented by simply updating memory contents rather than performing hardware modifications, thus eliminating hardware downtime during upgrades.
3Speed
If instruction decoding logic is integrated into the processor core, then processing speed is improved, but processor chip area increases
Solution Approach 1:
The patent segments the decoding logic into a separate decode stage that is coupled to the SIMD engine but can be independently configured. The decode stage receives instructions and generates control signals that address control memory locations, separating the decoding function from the core processing elements. This segmentation allows the processor core to remain compact while still providing fast processing through efficient control signal generation and retrieval from control memory.
Data Source
AI summary
An exemplary SIMD computing system comprises a SIMD processing element (SPE) configured to perform a selected operation on a portion of a processor input data word, with the operation selected by control signals read from a control memory location addressed by a decoded instruction. The SPE may comprise one or more adder, multiplier, or multiplexer coupled to the control signals. The control signals may comprise one or more bit read from the control memory. The control memory may be an M×N (M rows by N columns) memory having M possible SIMD operations and N control signals. Each instruction decoded may select an SPE operation from among N rows. A plurality of SPEs may receive the same control signals. The control memory may be rewritable, advantageously permitting customizable SIMD operations that are reconfigurable by storing in the control memory locations control signals designed to cause the SPE to perform selected operations.