SIMD Arithmetic Error Detection Using Single Vector Residue Codes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing SIMD arithmetic operations in modern processor architectures face high resource overhead due to traditional residue error checking methods, which require storing a residue code per data element, leading to significant costs in chip area and processing power.
Innovation Solution
Implementing a single residue code per SIMD packed vector, independent of its size, reduces the need for storing residue codes per data element, thereby saving resources and processing power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional residue error checking methods are used for SIMD arithmetic operations, then error detection capability is improved, but chip area and processing power costs increase significantly
Solution Approach 1:
The patent merges the residue codes of multiple data elements into a single aggregated residue code for the entire SIMD vector. Instead of maintaining separate residue codes for each data element (which would require 64 residue codes for a 512-bit vector with 8-bit elements), the invention combines them into one residue code, reducing the storage requirement from 128 bits to just 2 bits while preserving error detection capability across all elements in the vector.
Solution Approach 2:
The single aggregated residue code serves as a universal error detection mechanism for the entire SIMD vector regardless of its size. This universal approach allows the same residue checking mechanism to protect vectors of various widths (128-bit, 256-bit, 512-bit) without requiring proportional increases in residue code storage, making the error detection system scalable and efficient across different SIMD configurations.
2Reliability
If traditional residue error checking methods are used for SIMD arithmetic operations, then error detection capability is improved, but processing power costs increase
Solution Approach 1:
The patent merges the residue codes of multiple data elements into a single aggregated residue code for the entire SIMD vector. Instead of maintaining separate residue codes for each data element (which would require 64 residue codes for a 512-bit vector with 8-bit elements), the invention combines them into one residue code, reducing the storage requirement from 128 bits to just 2 bits while preserving error detection capability across all elements in the vector.
Solution Approach 2:
The single aggregated residue code serves as a universal error detection mechanism for the entire SIMD vector regardless of its size. This universal approach allows the same residue checking mechanism to protect vectors of various widths (128-bit, 256-bit, 512-bit) without requiring proportional increases in residue code storage, making the error detection system scalable and efficient across different SIMD configurations.
3Measurement precision
If residue code per data element is stored, then error detection precision is improved, but resource overhead increases
Solution Approach 1:
The patent merges the residue codes of multiple data elements into a single aggregated residue code for the entire SIMD vector. Instead of maintaining separate residue codes for each data element (which would require 64 residue codes for a 512-bit vector with 8-bit elements), the invention combines them into one residue code, reducing the storage requirement from 128 bits to just 2 bits while preserving error detection capability across all elements in the vector.
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
A method includes calculating, by a processor core, a first residue code of a first packed vector stored in a first vector register of a set of vector registers; calculating a second residue code of a second packed vector stored in a second vector register of the set of vector registers; calculating, from an addition of the first residue code and the second residue code, a reference residue code for a SIMD arithmetic operation; performing an element-by-element execution of the SIMD arithmetic operation between data elements of the first packed vector and of the second packed vector, resulting in an output packed vector; calculating an output residue code of the output packed vector; and detecting an error in the SIMD arithmetic operation based on comparison of the reference residue code with the output residue code.