SIMD Floating-Point Conversion to Fixed-Point Integer and Exponent

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Solution Overview

Problem

Current computer processors lack an efficient method to convert single precision floating-point values from packed data operands to fixed-point representations, particularly in SIMD operations, which limits data type conversions and precision handling.

Innovation Solution

The implementation of a floating-point to fixed-point convert instruction that processes a single precision floating-point value from a packed data source operand, converting it into a 32-bit integer and 32-bit exponent components, and storing these in the destination operand while zeroing other elements, utilizing execution circuitry to handle various operand sizes and memory locations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If floating-point to fixed-point conversion is implemented in software, then conversion capability is provided, but processing speed and efficiency are insufficient

Engineering Contradiction:
Improvedata type conversion capabilityVSAvoidprocessing speed
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent replaces software-based floating-point to fixed-point conversion with hardware execution circuitry that natively supports the conversion operation. The conversion instruction is implemented as a dedicated hardware function within the processor's execution units, eliminating the need for software interpretation and significantly improving processing speed while maintaining full conversion capability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Ease of operation

If general-purpose conversion methods are used, then basic conversion is possible, but precision handling and SIMD operation support are limited

Engineering Contradiction:
Improveconversion simplicityVSAvoidprecision handling
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent implements specialized execution circuitry within the processor that provides localized, optimized handling of floating-point to fixed-point conversion. The hardware includes dedicated logic for managing precision requirements and supporting SIMD operations, allowing different parts of the conversion process to be handled by specialized components rather than a general-purpose software routine.

Inventive Principle:
Principle #3Local quality

3Device complexity

If no dedicated conversion instruction is provided, then processor complexity is reduced, but data type conversion efficiency is limited

Engineering Contradiction:
Improveprocessor instruction setVSAvoidconversion efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the floating-point to fixed-point conversion function into a dedicated instruction format with specific opcode encoding. The conversion operation is separated from other arithmetic operations and implemented as a distinct hardware function, allowing the processor to efficiently execute conversions without the overhead of general-purpose arithmetic logic while maintaining a manageable instruction set architecture.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10763891B2Floating point to fixed point conversion
Publication Date: 2020.09.01 INTEL CORP
  • US10763891B2 patent drawing
  • US10763891B2 patent drawing
  • US10763891B2 patent drawing

AI summary

Embodiments of an instruction, its operation, and executional support for the instruction are described. In some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and execution circuitry to execute the decoded instruction to convert a single precision floating point data element of a least significant packed data element position of the identified packed data source operand to a fixed-point representation, store the fixed-point representation as 32-bit integer and a 32-bit integer exponent in the two least significant packed data element positions of the identified packed data destination operand, and zero of all remaining packed data elements of the identified packed data destination operand.