SIMD Floating Point Exception Handling via Packed Partial Results
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Solution Overview
Problem
Existing processors that execute SIMD instructions face inefficiencies in handling floating point exceptions, particularly with denormal numbers, leading to slower calculations compared to normal numbers.
Innovation Solution
The implementation of efficient techniques that include initiating SIMD micro-operations to generate packed partial results, denormalization, and normalization of pseudo internal floating point representations, allowing for transparent handling of exceptions without converting to scalar operations and requiring only a small number of additional micro-operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If denormal numbers are supported in hardware with wider internal representation, then floating point exception handling accuracy is improved, but processing speed deteriorates significantly
Solution Approach 1:
The patent segments the handling of denormal numbers by detecting them separately from normal floating point operations. When a denormal number is detected in the operand, the system branches to a special microcode routine that handles denormalization specifically, while normal operations continue through the standard fast path. This segmentation allows accurate denormal handling without slowing down normal operations.
Solution Approach 2:
The patent introduces an intermediary detection mechanism that identifies denormal numbers before they enter the main execution pipeline. This intermediary check allows the system to prepare appropriate handling routines in advance, converting denormal operands to a suitable internal representation before processing, thereby maintaining both accuracy and speed.
2Reliability
If denormal numbers are handled by trapping to software or microcode support, then floating point exception handling completeness is improved, but calculation speed deteriorates
Solution Approach 1:
The patent performs preliminary detection and preparation for denormal number handling within the hardware pipeline itself, before full microcode intervention is required. By pre-detecting denormal operands and preparing their internal representation, the system reduces the complexity and time required for subsequent microcode processing, thereby maintaining completeness while improving speed.
Solution Approach 2:
The patent implements a dynamic handling approach where the processing path adapts based on the detected operand type. Normal operations follow a fast execution path, while denormal operations dynamically transition to a specialized handling routine. This dynamic adaptation ensures complete handling of all cases while optimizing for the common fast path.
3Measurement precision
If scalar conversions are performed for denormal number handling, then floating point exception handling accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the denormalization functionality directly into the existing floating point execution unit hardware. By combining the detection, conversion, and processing functions within a unified hardware structure, the system achieves accurate denormal handling without adding separate complex conversion circuits, thereby improving accuracy while controlling device complexity.
Data Source
AI summary
Methods and apparatus are provided for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one example a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one example a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.