SIMD Horizontal FIR Filtering Without Repeated Data Alignment

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing processor architectures face inefficiencies in performing horizontal finite impulse response (FIR) filter operations due to the need for data alignment and the use of additional neighboring pixels, which hinders performance when filtering in the direction of data storage order in memory.

Innovation Solution

The implementation of packed FIR filter instructions that allow for parallel processing of pixels using SIMD (Single Instruction Multiple Data) operations, reducing the need for data alignment and optimizing performance by reusing products for different results, and efficiently handling filter operations in the direction of data storage order.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional horizontal FIR filter operations are performed on existing processor architectures, then filtering can be accomplished, but data alignment requirements and additional neighboring pixel access increase processing complexity and reduce performance

Engineering Contradiction:
Improvefiltering performanceVSAvoiddata alignment complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the horizontal FIR filter operation into distinct segments: data alignment, multiplication, and result accumulation. Each segment is handled by dedicated circuitry within the SIMD execution unit, allowing parallel processing of multiple pixels while managing alignment complexity systematically rather than as a monolithic operation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of parallelism by processing multiple pixels simultaneously using SIMD operations. The execution unit processes N pixels in parallel across N data lanes, transforming the traditionally sequential horizontal filter operation into a massively parallel operation that operates on vectors of pixel data rather than individual pixels

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If data alignment is performed for each horizontal filter operation, then correct filtering results are achieved, but processing speed is reduced due to repeated alignment operations

Engineering Contradiction:
Improvefiltering accuracyVSAvoidprocessing speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent performs data alignment as a preliminary action within the SIMD execution unit before the actual filtering computation. The alignment circuitry prepares the pixel data in the correct format and position upfront, so that subsequent multiplication and accumulation operations can proceed without interruption or additional alignment steps, maintaining both accuracy and speed

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If additional neighboring pixels are accessed for horizontal filtering, then complete filter convolution is achieved, but memory access complexity and time increase

Engineering Contradiction:
Improvefilter convolution completenessVSAvoidpixel access time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent merges the access to multiple neighboring pixels into a single SIMD memory access operation. Instead of accessing each pixel sequentially, the execution unit retrieves N pixels in parallel through a single memory access transaction, combining multiple data fetches into one unified operation that maintains convolution completeness while minimizing access time

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10749502B2Apparatus and method for performing horizontal filter operations
Publication Date: 2020.08.18 INTEL CORP
  • US10749502B2 patent drawing
  • US10749502B2 patent drawing
  • US10749502B2 patent drawing

AI summary

An apparatus and method for performing FIR filtering and blending operations. A processor comprising: a decode unit to decode a packed N-tap finite impulse response (FIR) filter instruction, the packed N-tap FIR filter instruction to indicate one or more source packed data operands comprising a plurality of packed data elements, at least 3 filter coefficients, and a destination storage location, the plurality of packed data elements comprising data from a signal to be filtered and the plurality of filter coefficients specifying a filter function to be applied; and an execution unit comprising an FIR unit coupled with the decode unit, the FIR unit, in response to the packed N-tap FIR filter instruction being decoded by the decode unit, to perform at least N−1 multiplications to generate at least N−1 products, each of the multiplications comprising one of the filter coefficients multiplied by one of the packed data elements, the execution unit to combine the at least N−1 products in accordance with a specified type of FIR filter being implemented to generate a result packed data element to be stored in the destination storage location.