Feature Sub-Image Detection on SIMD CPU Without Saturation Logic
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Solution Overview
Problem
Existing signal processing algorithms for feature sub-image detection and identification in digital images are inefficient in terms of power consumption and Bill of Material (BoM) cost when implemented on Digital Signal Processor (DSP) cores, which require extensive logic gates and chip area.
Innovation Solution
Implementing detection and identification algorithms on a Central Processing Unit (CPU) with Single Instruction Multiple Data (SIMD) instructions without saturation logic, reducing the need for DSP cores and optimizing BoM cost and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DSP core with saturation logic is used for feature detection and identification, then processing capability and reliability are improved, but BoM cost and power consumption increase
Solution Approach 1:
The invention extracts and removes the saturation logic component from the processor architecture. By implementing feature detection and identification algorithms on a CPU core without dedicated saturation logic, the patent eliminates the need for expensive DSP cores while maintaining processing capability through software-based saturation handling in the SIMD instruction set.
Solution Approach 2:
The CPU core with SIMD extensions is used for multiple purposes - general-purpose computing and specialized signal processing for feature detection. This multi-functional approach replaces the need for dedicated DSP cores, reducing BoM cost while maintaining the ability to process digital image data effectively.
2Reliability
If DSP core with saturation logic is used for feature detection and identification, then processing capability is improved, but BoM cost increases
Solution Approach 1:
The invention extracts and removes the saturation logic component from the processor architecture. By implementing feature detection and identification algorithms on a CPU core without dedicated saturation logic, the patent eliminates the need for expensive DSP cores while maintaining processing capability through software-based saturation handling in the SIMD instruction set.
Solution Approach 2:
The patent uses a standard CPU core with SIMD extensions instead of a specialized DSP core. This approach uses more common, less expensive processor architecture that can be manufactured at lower cost, sacrificing some hardware optimization for overall system cost reduction.
3Use of energy by moving object
If CPU with SIMD instructions without saturation logic is used, then BoM cost and power consumption are reduced, but achieving bit-exact results becomes challenging
Solution Approach 1:
The patent introduces an intermediary software layer that handles saturation logic through SIMD instructions. This software-based saturation handling acts as a mediator between the simple CPU hardware and the complex signal processing requirements, achieving bit-exact results without requiring hardware saturation logic.
Solution Approach 2:
The invention changes the approach from hardware-based saturation handling to software-based saturation handling. By using SIMD instructions with saturation capability in software, the patent achieves the same functional result with different implementation parameters, reducing hardware complexity while maintaining precision.
Data Source
AI summary
The present invention provides a system and method for detection and identification of feature sub-image in a given image. The system (100) comprises single CPY core with Single Instruction Multiple Data (SIMD) instruction set but the instructions lack saturation logic (101), wherein the software modules are implemented. Removing the logic hardware used to implement saturation in the SIMD instructions helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results without saturation logic. The power consumed using CPU without saturation logic in SIMD instruction is lesser than using Digital Signal Processing Instruction Set Architecture with saturation logic, thus giving value additions to platform SoC designers and makers for using low BoM cost solution.