SIMD Instruction Set Extension for Wide Scalar Pattern Matching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current bit-parallel pattern matching algorithms face inefficiencies when pattern lengths exceed the scalar register width, as there is no hardware that can efficiently support such algorithms beyond the scalar register width, leading to suboptimal performance in applications like network intrusion detection and business analytics.
Innovation Solution
The implementation of bit-parallel string match algorithms using single instruction multiple data (SIMD) hardware, where the pattern length is limited by the SIMD width of vector registers, allowing for extended pattern matches through an extension of the instruction set architecture (ISA), enabling instructions like VPSLLQQ and VPSRLQQ to perform shift operations on multiple data elements simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If bit-parallel pattern matching algorithms are used with conventional scalar registers, then processing efficiency is maintained for short patterns, but pattern length is limited by scalar register width
Solution Approach 1:
The patent transitions from scalar register operations to SIMD vector register operations, effectively adding a dimension of parallelism. By using wide vector registers (e.g., 256-bit, 512-bit) instead of narrow scalar registers (e.g., 64-bit), the system can process multiple pattern bits simultaneously, thereby extending the effective pattern length beyond the scalar register width while maintaining processing efficiency.
2Productivity
If SIMD hardware is used to extend pattern length beyond scalar register width, then processing efficiency improves for long patterns, but instruction set complexity increases
Solution Approach 1:
The patent segments the pattern matching task into multiple stages that can be executed using standard SIMD instructions. Instead of requiring a single complex instruction, the algorithm divides the pattern into chunks that fit within vector registers and processes them through a sequence of shift, OR, and comparison operations. This segmentation allows the use of existing SIMD instruction sets while achieving extended pattern length capability.
3Length of moving object
If byte arrays are used to simulate bitmasks for patterns exceeding register width, then pattern length is extended, but processing speed decreases
Solution Approach 1:
The patent merges multiple byte-array operations into unified SIMD vector operations. By loading multiple bytes into a single wide vector register and performing parallel bitwise operations across all elements simultaneously, the system combines the extended capacity of byte arrays with the high speed of hardware-accelerated vector operations, thereby maintaining processing speed while supporting longer patterns.
Data Source
AI summary
A processor includes an instruction decoder to receive an instruction having a first operand, a second operand, and a third operand, and an execution unit coupled to the instruction decoder to execute the instruction, the execution unit to individually perform a shift operation by at least one bit for each of a plurality of data elements stored in a storage location indicated by the second operand, for each of the data elements that has an overflow in response to the shift-left operation, to carry over the overflow into an adjacent data element based on a first bitmask obtained from the third operand, generating a final result, and to store the final result in a storage location indicated by the first operand.