SIMD Lane Program Counters for Divergent Branch Execution
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Solution Overview
Problem
Existing SIMD circuits face issues with deadlocks and reduced memory-level parallelism due to the use of a single program counter for multiple execution lanes, leading to serialized branch execution and increased hardware complexity and power consumption.
Innovation Solution
Implementing multiple program counters for each execution lane in a SIMD circuit, allowing independent progression through divergent points and using a lane selecting identifier to manage active lanes, thereby maintaining instruction fetch independence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single program counter is used for multiple execution lanes, then hardware complexity is reduced, but memory-level parallelism is reduced and deadlocks can occur
Solution Approach 1:
The patent divides the single program counter into multiple separate program counters, one for each execution lane. This segmentation allows each lane to independently track its own instruction pointer, enabling independent progression through divergent control flow paths while maintaining the SIMD architecture's parallel execution capabilities.
2Device complexity
If a single program counter is used for multiple execution lanes, then hardware complexity is reduced, but execution serialization occurs at branch points
Solution Approach 1:
By segmenting the program counter into lane-specific counters, each execution lane can independently fetch and execute instructions following its own control flow path. This eliminates the serialization bottleneck that occurs when a single program counter must be shared among all lanes, allowing parallel branches to execute simultaneously without waiting for a common instruction pointer.
3Reliability
If independent instruction fetching is implemented for each lane, then memory-level parallelism is improved, but hardware complexity and power consumption increase
Solution Approach 1:
The patent implements independent instruction fetching by providing separate program counters for each execution lane, which independently track and fetch instructions. This segmentation approach enables each lane to autonomously manage its instruction stream, improving memory-level parallelism while keeping the hardware modifications localized to the program counter mechanism rather than requiring complete hardware redesign.
Data Source
AI summary
An apparatus and method for efficiently processing instructions in hardware parallel execution lanes. In various implementations, a computing system includes a processing circuit that uses a single instruction multiple data (SIMD) circuit that maintains multiple program counter values for multiple parallel lanes of execution. If a divergent point has been reached in the application, then the SIMD circuit generates a lane selecting identifier specifying one of the parallel lanes of execution that remains active to execute the taken path of the divergent point. The SIMD circuit continues executing with each of the parallel lanes of execution with a program counter that matches a program counter of the parallel lane of execution pointed to by the lane selecting ID. The SIMD circuit switches lanes from being inactive to active after a threshold amount of time has elapsed. The SIMD circuit also performs other steps to increase memory-level parallelism.