SIMD Lookup Table Interpolation for Real-Time Digital Pre-Distortion

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing computer architectures with Single Instruction Multiple-Data (SIMD) processors face challenges in efficiently compensating for power amplifier distortion in wireless communication devices, particularly due to the large number of possible lookup values required for accurate digital pre-distortion, which exceeds the capacity of local memory in Arithmetic Units (AUs).

Innovation Solution

The implementation of a SIMD processor system with a vector processor unit (VPU) that executes table transfer and lookup instructions, allowing each AU to access and interpolate values from lookup tables stored in local memory, reducing the need for extensive local memory storage by using interpolation to determine interpolated resultants for digital pre-distortion calculations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If lookup tables are stored in local memory of each Arithmetic Unit for fast access, then processing speed is improved, but memory capacity requirements increase beyond what local memory can provide

Engineering Contradiction:
Improveprocessing speedVSAvoidmemory capacity
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent divides the lookup table data into multiple segments or blocks that are stored in global memory. Each Arithmetic Unit processes a specific segment of data, accessing only the relevant portion of the lookup table needed for its computation. This segmentation allows fast local processing while reducing the memory burden on each individual Arithmetic Unit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a hierarchical memory structure where small lookup tables are cached in the local memory of each Arithmetic Unit, while the complete lookup tables reside in global memory. The local memory acts as a nested cache within the broader global memory system, allowing Arithmetic Units to quickly access frequently used data while maintaining access to the full dataset through the global memory interface.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Measurement precision

If all possible lookup values are stored to ensure accurate digital pre-distortion, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improvedigital pre-distortion accuracyVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent pre-calculates and stores distortion compensation values in lookup tables during a calibration phase, before actual signal processing occurs. These pre-computed values are organized in a structured format that allows efficient access during real-time operation. By performing the complex calculation work in advance, the system achieves high precision distortion compensation without requiring complex real-time computation resources.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates simplified representations of the distortion characteristics by copying essential data into compact lookup table formats. Instead of storing or processing all possible distortion scenarios in full detail, the system uses representative sampled values that capture the essential distortion behavior, reducing complexity while maintaining sufficient accuracy for practical applications.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS10261939B2Performing lookup table operations on a single-instruction multiple data processor
Publication Date: 2019.04.16 NXP USA INC
  • US10261939B2 patent drawing
  • US10261939B2 patent drawing
  • US10261939B2 patent drawing

AI summary

In accordance with at least one embodiment, a processor system is disclosed having a SIMD processor device that has a plurality of subsidiary processing elements that are controlled to process multiple data concurrently. In accordance with at least one embodiment, the SIMD processor is a vector processor (VPU) having a plurality of vector Arithmetic Units (AUs) as subsidiary processing elements, and the VPU executes an instruction to transfer table information from a global memory of the VPU to a plurality of local memories accessible by each AU. The VPU also executes an instruction that results in each processing element performing a table lookup from a table stored at its local memory. In response to the instruction, this table lookup uses a portion of a lookup value to access information from the table, and uses another portion of the lookup information to calculate an interpolated resultant based upon the accessed information.