SIMD LPHDR Arithmetic for Massively Parallel Computing
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Solution Overview
Problem
Conventional CPU architectures are inefficient in utilizing the vast number of transistors available, as they are designed to provide high precision arithmetic, leading to underutilization of computing power.
Innovation Solution
The use of Low Precision High Dynamic Range (LPHDR) processing elements in SIMD computing systems, which perform arithmetic operations with a precision of about 0.1%, allowing for a greater number of operations per unit of time or power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional CPU architectures use high precision arithmetic to ensure calculation accuracy, then measurement precision is improved, but productivity deteriorates due to underutilization of available transistors
Solution Approach 1:
The patent changes the precision parameter from conventional high precision (e.g., 32-bit or 64-bit floating point) to low precision (e.g., 8-bit or 16-bit integers with controlled error bounds). This parameter change allows massively parallel arithmetic operations to be performed using simple integer arithmetic, thereby resolving the contradiction between precision and productivity by achieving acceptable accuracy through alternative computational approaches
Solution Approach 2:
The patent employs numerous low-cost, low-precision processing elements that can be massively replicated on a single chip. These inexpensive computational units perform approximate arithmetic operations with controlled error margins, enabling high productivity through parallelism while maintaining sufficient accuracy for many applications without requiring expensive high-precision hardware
2Measurement precision
If conventional CPU architectures prioritize high precision arithmetic operations, then measurement precision is improved, but use of energy worsens due to the complexity of precision arithmetic circuits
Solution Approach 1:
The patent changes the arithmetic precision parameter to low precision integer arithmetic, which requires significantly less energy per operation. By using simple integer addition, subtraction, and bit-shifting operations instead of complex floating-point arithmetic, the system achieves acceptable computational accuracy while dramatically reducing energy consumption per computational operation
Solution Approach 2:
The patent uses numerous inexpensive, low-power processing elements that perform approximate arithmetic with controlled error bounds. These low-precision units consume far less energy than high-precision units while collectively providing sufficient computational power through parallelism, thereby resolving the contradiction between precision and energy usage
3Measurement precision
If conventional CPU architectures are designed for high precision arithmetic, then measurement precision is improved, but device complexity increases due to the requirements for precise arithmetic circuits
Solution Approach 1:
The patent changes the arithmetic precision parameter from high to low, replacing complex floating-point arithmetic circuits with simple integer arithmetic circuits. This parameter change dramatically reduces circuit complexity while maintaining sufficient computational accuracy through controlled error bounds and parallel processing
Solution Approach 2:
The patent employs many simple, low-complexity processing elements that perform approximate arithmetic operations. These inexpensive computational units with reduced circuit complexity can be massively replicated on a single chip, resolving the contradiction between precision and device complexity by achieving sufficient accuracy through parallelism rather than individual unit precision
4Measurement precision
If conventional CPU architectures use high precision arithmetic operations, then measurement precision is improved, but productivity deteriorates due to the limited number of operations per cycle
Solution Approach 1:
The patent changes the precision parameter to low precision, enabling the use of simple integer arithmetic operations that can be executed in parallel. This parameter change allows hundreds or thousands of arithmetic operations to be performed per clock cycle through SIMD parallelism, resolving the contradiction between precision and productivity by achieving acceptable accuracy through massive parallelism rather than sequential high-precision operations
Solution Approach 2:
The patent segments the computational task into many independent parallel operations performed by multiple low-precision processing elements. By dividing the computation into numerous simple integer arithmetic operations that can be executed simultaneously, the system achieves high productivity while maintaining sufficient accuracy through the collective result of many parallel operations
Data Source
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AI summary
A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (including one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range ("LPHDR arithmetic"). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).