SIMD Mask Array Generation for Loop Parallelization
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Solution Overview
Problem
In High Performance Computing (HPC) environments, existing methods for parallelizing nested loops in shared memory systems face inefficiencies when the number of iterations is less than the number of CPU cores, leading to suboptimal use of hardware performance, and the use of SIMD instructions with masks results in increased memory usage due to large mask data amounts.
Innovation Solution
An information processing apparatus that converts nested loops into single loops, expands the iteration space to a power-of-two number of elements, and generates a second mask array with fewer masks by using bitwise logical operations to specify computation for elements, allowing efficient SIMDization without excessive memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If masks are prepared for all elements to be accessed in SIMD instruction, then computation precision is improved, but memory capacity consumption increases
Solution Approach 1:
The mask array is segmented into multiple smaller mask arrays, where each mask array manages a specific portion of the elements. This segmentation reduces the memory footprint of individual mask arrays while maintaining comprehensive coverage through multiple arrays, directly resolving the contradiction between precision and memory consumption.
Solution Approach 2:
The patent introduces a new dimension to mask management by organizing masks into multiple arrays with different scopes (first mask array for all elements, second mask array for specific portions). This dimensional organization allows selective application of masks, reducing overall memory consumption while preserving computation precision where needed.
2Productivity
If nested loop is converted to single loop with expanded iteration space, then parallelization efficiency is improved, but processing complexity increases
Solution Approach 1:
The processing is segmented into distinct phases: loop conversion phase, mask generation phase, and execution phase. Each phase handles specific tasks independently, reducing overall processing complexity while maintaining parallelization efficiency. The segmentation allows complex operations to be broken down into manageable, reusable components.
Solution Approach 2:
Masks are generated in advance during the mask generation phase, before the actual computation execution. This preliminary action prepares the mask structures ahead of time, reducing the complexity of runtime processing while enabling efficient parallel execution in the subsequent phase.
3Quantity of substance
If mask data amount is reduced by using repeating patterns, then memory usage is improved, but expression complexity increases
Solution Approach 1:
The mask management is segmented into hierarchical levels: a first mask array covering all elements and second mask arrays covering specific portions. This segmentation allows the system to use compact representations where applicable while maintaining full precision where needed, balancing memory efficiency with expression simplicity.
Solution Approach 2:
Instead of applying complex pattern repetition to all elements, the patent applies detailed mask management only to specific portions where needed (second mask array), while using simpler management for the remainder (first mask array). This partial action approach reduces overall expression complexity while maintaining memory efficiency.
Data Source
AI summary
An information processing apparatus sets, in a second program: a second array where an occurrence pattern indicating whether elements are subjected to computation is a repetition of a pattern for every power-of-two number of elements; a second mask array generated by adding masks indicating that corresponding elements are not subjected to the computation to a first mask array so that the second mask array includes as many masks as the number of elements included in a second pattern; and a second instruction string providing an instruction for the computation of elements corresponding to masks indicating that corresponding elements are subjected to the computation, among the elements set in the second array. Each mask in the second mask array to be applied to an element in the second array is specified by a bitwise logical AND using a value indicating the position of the element in the second array.