Configurable SIMD Multiplication Circuit Using Radix-N Booth Encoding
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Solution Overview
Problem
Conventional multiplication circuits in processors face inefficiencies when performing multiplications across a range of data element sizes due to complex logic requirements for higher radix Booth multiplication, which is unsuitable for configurable SIMD environments.
Innovation Solution
A configurable SIMD multiplication circuit using radix-N modified Booth multiplication with N=2P and P≥3, where the Booth digit selection process is adjusted to simplify the implementation, allowing for efficient performance across various data element sizes by partitioning larger operands into smaller Emin-bit portions and applying Booth encoding separately to each portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If radix-N modified Booth multiplication is used with higher radix (N≥8), then multiplication performance is improved, but circuit complexity and area increase
Solution Approach 1:
The patent partitions larger operands into smaller Emin-bit portions and applies Booth encoding separately to each portion. This segmentation allows the complex high-radix multiplication to be broken down into manageable segments that can be processed independently, reducing the overall circuit complexity while maintaining high multiplication performance
Solution Approach 2:
The patent applies different encoding strategies to different parts of the operand based on their position and significance. By using local quality variations in the encoding approach for different Emin-bit portions, the circuit achieves optimized performance without uniformly increasing complexity across the entire multiplication circuit
2Adaptability or versatility
If configurable SIMD multiplication is implemented to support multiple element sizes, then versatility is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal multiplication circuit that can handle multiple element sizes (8-bit, 16-bit, 32-bit, etc.) through a single unified architecture. By designing the circuit to be element-size-agnostic and using configurable parameters, the same hardware structure serves multiple functions across different data widths, improving versatility without proportionally increasing complexity
Solution Approach 2:
The patent introduces dynamic configurability where the multiplication circuit can adapt its operation based on the selected element size. Control logic dynamically adjusts the Booth encoding parameters and operand partitioning based on the configured element size, allowing the circuit to optimize its behavior for each specific configuration rather than being statically designed for one size
3Loss of time
If higher radix Booth multiplication is used, then the number of partial products is reduced, but logic requirements increase
Solution Approach 1:
The patent changes the radix parameter from conventional values to higher values (N≥8) in the Booth multiplication algorithm. This parameter change reduces the number of partial products that need to be generated and added, directly reducing multiplication time. The circuit is specifically designed to handle these higher radix parameters efficiently through customized encoding logic
Data Source
AI summary
A configurable SIMD multiplication circuit is provided to perform multiplication on a multiplicand operand M and multiplier operand R with varying data element sizes supported. For each result element generated based on corresponding elements of the multiplicand operand M and the multiplier operand R, the multiplication is performed according to radix-N modified Booth multiplication, where N=2P and P≥3. A Booth digit selection scheme is described for improving the efficiency with which higher radix modified Booth multiplication can be implemented in a configurable SIMD multiplier.