SIMD Multiplier-Accumulator Unit for High-Throughput Variable Precision Operations
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Solution Overview
Problem
Existing hardware-based binary multipliers face challenges in efficiently performing high-throughput multiply-accumulate operations with variable precision data, requiring minimal power consumption and avoiding accumulator overflow, while handling both signed and unsigned inputs and various data formats.
Innovation Solution
A SIMD digital hardware multiplier-accumulator apparatus with 16-bit by 32-bit multiplier circuits using carry-save addition and a 3:2 Wallace tree compressor, along with a carry propagate adder, to generate partial products and prevent overflow, while supporting flexible data formats and sign extension management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general-purpose processors are used to perform multiply-accumulate operations, then flexibility and programmability are maintained, but throughput and execution speed deteriorate
Solution Approach 1:
The processor is segmented into distinct execution units: a general-purpose processor for control and a dedicated SIMD multiplier-accumulator unit for high-throughput computation. The multiply-accumulate operations are segmented into multiple parallel lanes that can simultaneously process different data elements, achieving both flexibility through software control and high throughput through hardware parallelism
Solution Approach 2:
A dedicated SIMD multiplier-accumulator unit acts as an intermediary between the general-purpose processor and the data streams. This intermediary handles the computationally intensive multiply-accumulate operations in hardware while the general-purpose processor maintains control through instruction issuance and data provisioning, resolving the throughput-flexibility tradeoff
2Productivity
If dedicated hardware multiplier-accumulator units are used, then throughput is improved, but power consumption and circuit area increase
Solution Approach 1:
The SIMD multiplier-accumulator unit performs slightly more operations than minimally required by including additional parallel lanes and a wide accumulator. This partial excess enables the unit to handle variable precision data formats and accumulate results across multiple operations without overflow, while the overhead is justified by the elimination of overflow handling logic and increased operational throughput
Solution Approach 2:
The multiplier-accumulator unit is designed with universal functionality to handle multiple data formats (8-bit, 16-bit, 24-bit, 32-bit) and both signed and unsigned operations through configurable input formats and sign extension logic. This multi-functionality reduces the need for multiple specialized units, thereby reducing overall power consumption and circuit area
3Reliability
If accumulator data width is increased to prevent overflow, then reliability is improved, but hardware complexity and delay increase
Solution Approach 1:
The accumulator is pre-configured with sufficient data width (e.g., 64-bit or wider) to accommodate the maximum possible accumulation result before overflow can occur. This preliminary sizing prevents overflow conditions entirely, eliminating the need for complex overflow detection and handling logic during operation, thereby improving reliability without proportionally increasing hardware complexity
Solution Approach 2:
The accumulator width parameter is optimized to the minimum necessary value that prevents overflow for the specific application's data range and operation count. By carefully selecting this parameter based on statistical analysis of the workload, the design achieves reliable overflow prevention while minimizing the hardware resources required for the accumulator
4Adaptability or versatility
If configurable data formats are supported, then adaptability is improved, but device complexity increases
Solution Approach 1:
The multiplier-accumulator unit incorporates dynamic configuration capabilities where the data format (8-bit, 16-bit, 24-bit, 32-bit) and sign handling can be adjusted through control signals for each operation. This dynamic adaptability allows the same hardware to efficiently process different data formats without requiring multiple dedicated units, balancing versatility with manageable hardware complexity through reconfigurable logic
Data Source
AI summary
A single-instruction multiple-data (SIMD) multiplier-accumulator apparatus and method. A multiplier block with two 16-bit by 32-bit multiplier circuits transform a selectable number of input multipliers and multiplicands into a selected number of products. Each multiplier circuit comprises an array of full adders that generates and sums partial products using carry-save addition. An accumulator block, with additional data width to help prevent overflow, adds the products to a selectable number of input addends and outputs a number of results. Embodiments perform one to four multiplications together, depending on the number of bits (eight, 16, 24, or 32) selected for the input operands. Embodiments output 20-bit, 40-bit, or 80-bit multiply-accumulate results at rates of at least 1.1 GHz. Embodiments support signed inputs, negated multiplication products, and Q-format data. A hybrid sign extension management approach improves performance for 80-bit outputs.