SIMD Permutation Circuitry Bypass for Reduced Processing Cycles
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Solution Overview
Problem
Existing SIMD processing units require additional cycles for data element rearrangement, even when it's not necessary, due to combining permutation and SIMD operations into a single multi-cycle operation, which penalizes all SIMD operations and increases processing time.
Innovation Solution
Incorporating separate permutation circuitry and SIMD processing circuitry controlled independently by an instruction decoder, allowing permutation operations to be isolated from SIMD operations and only performed when required, thus enabling faster execution of SIMD instructions without unnecessary rearrangement cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If permutation circuitry is integrated into the SIMD processing pipeline for all operations, then data rearrangement capability is improved, but processing cycles increase for all SIMD operations including those not requiring permutation
Solution Approach 1:
The patent segments the SIMD processing pipeline into distinct permutation circuitry and SIMD processing circuitry components. The permutation circuitry is configured as a separate stage that can be selectively activated based on whether permutation is required, rather than being a mandatory sequential step for all operations. This segmentation allows the system to avoid unnecessary permutation overhead while maintaining full permutation capability when needed.
Solution Approach 2:
The patent implements dynamic control of the permutation circuitry through instruction decoder logic that analyzes incoming SIMD instructions. When a SIMD instruction does not require permutation, the control logic dynamically bypasses the permutation circuitry stage, allowing the operand to proceed directly to the SIMD processing circuitry. This dynamic activation/bypass mechanism optimizes processing cycles by adapting the pipeline execution path to the specific requirements of each instruction.
2Device complexity
If permutation operation is combined with SIMD operation in a single multi-cycle operation, then operational integration is improved, but average processing speed decreases due to unnecessary rearrangement cycles
Solution Approach 1:
The patent separates the permutation operation and SIMD operation into distinct functional stages with independent control. The permutation circuitry and SIMD processing circuitry are implemented as separate modules that can be activated independently based on instruction requirements. This segmentation eliminates the mandatory multi-cycle overhead while preserving the capability to perform both operations when needed, thereby improving average processing speed without sacrificing operational integration capability.
Solution Approach 2:
The patent applies local quality optimization by providing different processing paths for different instruction types. Instructions requiring permutation follow a path that includes the permutation circuitry stage, while instructions not requiring permutation follow a streamlined path that bypasses this stage. This localized optimization ensures that each instruction type receives the appropriate level of processing without being penalized by unnecessary operations, thus improving overall productivity.
Data Source
AI summary
A data processing apparatus has permutation circuitry for performing a permutation operation for changing a data element size or data element positioning of at least one source operand to generate first and second SIMD operands, and SIMD processing circuitry for performing a SIMD operation on the first and second SIMD operands. In response to a first SIMD instruction requiring a permutation operation, the instruction decoder controls the permutation circuitry to perform the permutation operation to generate the first and second SIMD operands and then controls the SIMD processing circuitry to perform the SIMD operation using these operands. In response to a second SIMD instruction not requiring a permutation operation, the instruction decoder controls the SIMD processing circuitry to perform the SIMD operation using the first and second SIMD operands identified by the instruction, without passing them via the permutation circuitry.