SIMD Polynomial Coding for Large-Drive Error Recovery

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Solution Overview

Problem

Existing error-correcting codes are limited in their ability to handle large numbers of drives and provide efficient error recovery, particularly in RAID systems where traditional Vandermonde encoding matrices are restricted to 14 drives or fewer.

Innovation Solution

The use of polynomial codes generated by a linear feedback shift register (LFSR) or matrices generated by an LFSR, which support both erasure coding and unknown error decoding, enabling efficient error recovery and system reliability even with large numbers of drives.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional Vandermonde encoding matrices are used, then encoding and decoding can be performed, but the system is limited to 14 drives or fewer

Engineering Contradiction:
Improvenumber of drivesVSAvoiderror correction capability
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent changes the mathematical parameters of the encoding scheme by using polynomial codes with LFSR-generated matrices instead of traditional Vandermonde matrices. This parameter change enables the system to handle 255 drives or more while maintaining error correction capability, directly resolving the contradiction between drive quantity and error correction versatility.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If more check disks are added to increase reliability, then more drive failures can be withstood, but system cost increases

Engineering Contradiction:
Improvedrive failure toleranceVSAvoidnumber of components
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent changes the encoding parameters to use polynomial codes that provide higher error correction efficiency. This allows the system to achieve the same or better reliability with fewer check disks compared to traditional Vandermonde-based systems, thus reducing the total number of components while maintaining or improving drive failure tolerance.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If polynomial codes with LFSR are used, then error correction capability is improved, but computational complexity increases

Engineering Contradiction:
Improveerror decoding capabilityVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces complex general-purpose polynomial decoding computations with a specialized LFSR-based decoding mechanism. The LFSR structure provides inherent computational efficiency for polynomial operations, substituting complex arithmetic operations with simpler shift and XOR operations, thereby reducing computational complexity while maintaining error correction capability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

4Quantity of substance

If larger groups of data drives are created, then fewer overall components are needed, but error recovery becomes more difficult

Engineering Contradiction:
Improvetotal component countVSAvoiderror recovery difficulty
Core Design Contradiction:
Quantity of substanceVSDifficulty of detecting and measuring

Solution Approach 1:

The patent changes the encoding parameters to use polynomial codes with LFSR-generated matrices that are specifically designed to maintain efficient decoding performance even as the number of data drives increases to 255 or more. This parameter change allows large drive groups to be formed with reduced total component count while keeping error recovery difficulty manageable through the mathematical properties of LFSR-based codes.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12341532B2Accelerated polynomial coding system and method
Publication Date: 2025.06.24 STREAMSCALE INC
  • US12341532B2 patent drawing
  • US12341532B2 patent drawing
  • US12341532B2 patent drawing

AI summary

A system using accelerated error-correcting code in the storage and retrieval of data, wherein a single-instruction-multiple-data (SIMD) processor, SIMD instructions, non-volatile storage media, and an I/O controller implement a polynomial coding system including: a data matrix including at least one vector and including rows of at least one block of original data; a check matrix including more than two rows of at least one block of check data in the main memory; and a thread that executes on a SIMD CPU core and including: a parallel multiplier that multiplies the at least one vector of the data matrix by a single factor; and a parallel linear feedback shift register (LFSR) sequencer or a parallel syndrome sequencer configured to order load operations of the original data into at least one vector register of the SIMD CPU core and respectively compute the check data or syndrome data with the parallel multiplier.