SIMD Re-arrangement Instruction for Code Density
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Solution Overview
Problem
Existing SIMD data processing systems face inefficiencies in code density and power consumption due to the need for multiple instructions to perform complex data re-arrangements, particularly in operations like FFT processes, where separate code sections are required for each stage, leading to increased code size and power usage.
Innovation Solution
A data processing apparatus and method that utilizes a re-arrangement instruction set, where scalar processing logic provides parameters to SIMD processing logic to perform a family of re-arrangement operations, such as interleave, de-interleave, transpose, and reverse, allowing a single loop to execute different operations based on changing data element widths, thereby improving code density and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple separate instructions are used to perform different data re-arrangement operations in SIMD processing, then the required data re-arrangements can be achieved, but the code density decreases and power consumption increases
Solution Approach 1:
The patent implements a universal re-arrangement instruction that can perform multiple different data re-arrangement operations (interleave, de-interleave, transpose, reverse) by accepting control parameters that specify the operation type. This single multi-functional instruction replaces what would otherwise require multiple separate instructions, thereby improving code density while maintaining full re-arrangement capability.
Solution Approach 2:
The patent uses parameter-based control to differentiate between various re-arrangement operations. By changing the control parameters (such as operation type codes and data element width specifications) passed to the same re-arrangement instruction, the system can dynamically perform different re-arrangement functions without requiring separate instruction sequences for each operation.
2Adaptability or versatility
If multiple separate code sections are used for each stage of FFT processing, then the required data manipulations can be performed, but power consumption increases due to reduced cache efficiency
Solution Approach 1:
The patent applies the universal re-arrangement instruction to FFT processing stages, where a single code loop can perform different data manipulations required at each FFT stage by varying the control parameters. This consolidates multiple separate code sections into one reusable loop, improving cache line reuse and reducing power consumption while maintaining the ability to perform stage-specific manipulations.
Solution Approach 2:
The patent structures FFT processing to reuse the same code loop periodically across different stages, with control parameters being updated for each iteration. This periodic reuse of the same instruction sequence improves cache efficiency compared to having separate code sections for each stage, thereby reducing power consumption.
3Speed
If data elements are packed into SIMD registers for parallel processing, then processing speed increases, but significant re-ordering time is required which negates the performance benefit
Solution Approach 1:
The patent performs data re-arrangement operations using the universal re-arrangement instruction immediately before SIMD processing operations, ensuring data is in the correct format when needed. By consolidating re-arrangement into a single efficient operation rather than multiple sequential operations, the preliminary preparation time is minimized, preserving the performance benefits of SIMD parallel processing.
Data Source
AI summary
An apparatus and method are provided for performing re-arrangement operations on data. The data processing apparatus has a register data store with a plurality of registers for storing data, and processing logic for performing a sequence of operations on data including at least one re-arrangement operation. The processing logic has scalar processing logic for performing scalar operations and SIMD processing logic for performing SIMD operations. The SIMD processing logic is responsive to a re-arrangement instruction specifying a family of re-arrangement operations to perform a selected re-arrangement operation from that family on a plurality of data elements constituted by data in one or more registers identified by the re-arrangement instruction. The selected re-arrangement operation is dependent on at least one parameter provided by the scalar processing logic, that parameter identifying a data element width for the data elements on which the selected re-arrangement operation is performed. By such an approach, significant code density improvements can be made in respect of the code executed by the SIMD processing logic.