SIMD Register Data Loading for Database Predicate Evaluation
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Solution Overview
Problem
Current database systems face inefficiencies in processing large datasets due to limitations in how data is filtered and processed within CPU registers, particularly when handling complex queries and predicates, which can lead to suboptimal performance and increased computation time.
Innovation Solution
The implementation of Single Instruction Multiple Data (SIMD) registers and iterative evaluation techniques allows for parallel processing of data elements, enabling efficient filtering and processing of large datasets by dividing data into sections that align with SIMD register sizes, thereby optimizing the execution of queries and predicates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is processed using traditional CPU instructions sequentially, then the processing logic is simple and easy to implement, but the computation time increases and processing speed decreases
Solution Approach 1:
The patent segments data into fixed-size blocks that align with SIMD register widths (e.g., 128-bit, 256-bit, 512-bit registers). Each block is processed independently through parallel operations, allowing multiple data elements to be handled simultaneously within a single instruction cycle, thereby increasing processing speed without requiring complex control logic
Solution Approach 2:
The patent merges multiple data elements into a single SIMD register for parallel processing. By combining multiple scalar operations into one vectorized instruction, the system achieves higher throughput while maintaining relatively simple instruction semantics that can be implemented through standard SIMD extensions
2Productivity
If data is loaded entirely into SIMD registers for processing, then computation speed improves through parallel operations, but memory bandwidth consumption increases and data transfer time increases
Solution Approach 1:
The patent divides large datasets into smaller chunks that fit within SIMD register capacity. Data is loaded in segments rather than all at once, allowing the system to process multiple smaller batches in parallel. This segmentation reduces the memory bandwidth required for each individual load operation while maintaining high computational throughput through efficient use of register resources
Solution Approach 2:
The patent performs preliminary data preparation by organizing data into SIMD-friendly formats and pre-loading necessary data into registers before execution. This preliminary organization minimizes the need for repeated memory accesses during computation, reducing overall memory bandwidth consumption while maximizing computational efficiency
3Loss of time
If the CPU processes data in smaller register-sized sections iteratively, then the processing becomes more efficient and computation time decreases, but the control logic and data management complexity increases
Solution Approach 1:
The patent implements automatic segmentation of data into fixed-size blocks that match SIMD register widths. The system iterates through these pre-segmented blocks using simple loop constructs, which reduces computation time through parallel processing while keeping control logic relatively straightforward. The segmentation is handled systematically rather than requiring complex dynamic management
Solution Approach 2:
The patent changes the parameter of data organization from arbitrary formats to fixed-size blocks aligned with SIMD register boundaries. This parameter change enables efficient iterative processing with simple control logic, as the fixed block size allows for predictable memory access patterns and straightforward loop-based iteration without requiring complex data management
4Ease of manufacture
If traditional scalar processing is used, then memory access patterns are simple, but the bandwidth utilization of the I/O path between CPU and memory is inefficient
Solution Approach 1:
The patent merges multiple scalar data accesses into single SIMD vector loads and stores. By combining multiple memory access operations into unified vectorized operations, the system improves I/O bandwidth utilization while maintaining relatively simple implementation through standard SIMD instructions that follow straightforward memory access patterns
Data Source
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AI summary
Executable code is generated for processing a request including a predicate associated with a column of a database table. The executable code defines how to process data through a register at the processor associated with single instructions on multiple data. When a number of bit values of the register at the processor is not an aliquot part of a count of rows in the column of the database table, a new column is loaded in the main memory to include the column of the database table and additional number of data elements. The number of bit values of a register section of the register is an aliquot part of a number of elements of the new column. The new loaded column is evaluated iteratively to determine result bit vectors to be loaded in the register. At the processor, result data is determined to correspond to the evaluated section.