SIMD Register Extension for Addressing Modes
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Solution Overview
Problem
SIMD processors face challenges in supporting specialized addressing modes like circular and bit-reversed addressing without increasing opcode space, limiting their functionality and performance in data processing applications.
Innovation Solution
The introduction of index and displacement form vector load/store instructions that utilize the extension portion of general-purpose registers to provide additional addressing control, allowing for increased functionality without expanding opcode size, by using the main portion for base addresses and the extension portion for control information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If load and store instructions use traditional addressing modes with large displacements, then addressing capability is sufficient, but opcode space is consumed and no room remains for additional functionality
Solution Approach 1:
The register file is segmented into a main portion and an extension portion. The main portion stores base addresses while the extension portion stores addressing mode control information. This segmentation allows the system to support multiple addressing modes without requiring separate opcodes for each mode, as the control information is embedded in the register extension rather than the instruction opcode.
2Productivity
If vector processors use N vector registers with M elements each, then parallel processing capability increases, but hardware complexity and cost increase
Solution Approach 1:
The scalar general purpose register is enhanced with an extension portion that provides multiple functions: storing base addresses, storing index values, and storing addressing mode control information. This multi-functional register design allows the processor to perform vector operations with specialized addressing modes using the same hardware resources, avoiding the need for separate vector register files and reducing overall hardware complexity.
Data Source
AI summary
Executing a first memory access instruction with update by an N-bit processor includes accessing at least one source register of a plurality of registers, wherein the accessing includes accessing a first register, wherein each register of the plurality of registers includes a main portion of N bits and an extension portion of M bits, wherein the main portion of the first register includes a first address operand. The execution of the first instruction further includes forming a memory access address using the first address operand; using the memory access address as an address for a memory access; producing an updated address operand; and writing the updated address operand to the main portion of the first register. The producing includes accessing an extension portion of a source register of the at least one source register to obtain modifying information and using the modifying information in the producing an updated address operand.