SIMD Processing Circuitry for SHA Hash Value Generation
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Solution Overview
Problem
Existing data processing systems face inefficiencies in executing cryptographic operations like SHA algorithms due to the need for large state data manipulation, which increases execution time and energy consumption, and the complexity of integrating special purpose cryptographic hardware with general purpose processors.
Innovation Solution
The use of single instruction multiple data (SIMD) processing mechanisms, specifically reusing the SIMD register file with iterative program instructions that process large data widths, allowing for parallel processing of hash value generation and schedule updates, thereby optimizing the execution of SHA algorithms like SHA-1, SHA-256, and SHA-224 without the need for dedicated cryptographic hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If general purpose processor executing general purpose instruction is used, then device complexity is reduced, but execution time and energy consumption increase
Solution Approach 1:
The SIMD register file and processing circuitry are designed to perform both traditional SIMD operations and cryptographic hash operations. The same hardware resources (register file, processing circuitry) are reused for multiple purposes, allowing the processor to handle cryptographic algorithms without adding dedicated cryptographic hardware, thus reducing device complexity while maintaining execution efficiency
Solution Approach 2:
The invention changes the operational parameters of the SIMD register file by allowing it to store and manipulate unusually long operand values (beyond traditional SIMD widths) specifically for cryptographic operations. This parameter change enables the existing hardware to efficiently handle the large state data required by hash algorithms like SHA-256 and SHA-512
2Loss of time
If special purpose cryptographic support processor is used, then execution time is reduced, but device complexity and integration difficulty increase
Solution Approach 1:
Instead of adding dedicated cryptographic hardware, the invention makes the existing SIMD processing units multi-functional by programming them to execute cryptographic algorithms. The same processing circuitry and register file that handle graphical and computational tasks are reused for cryptographic hash operations, eliminating the need for separate cryptographic processors while maintaining performance
Solution Approach 2:
The SIMD processing circuitry serves itself by being programmed to perform cryptographic operations. The existing hardware resources automatically handle both their traditional functions and cryptographic computations without requiring separate dedicated circuits, reducing overall device complexity while maintaining execution efficiency
3Productivity
If special purpose cryptographic hardware is integrated, then cryptographic processing speed improves, but integration complexity with interrupt handling and multitasking increases
Solution Approach 1:
The SIMD processing units serve dual purposes: traditional SIMD operations and cryptographic hash computations. Since these are general-purpose processing units already integrated into the processor core, they inherit the processor's existing interrupt handling and multitasking capabilities without requiring separate integration mechanisms, thus avoiding additional integration complexity
Solution Approach 2:
The invention merges cryptographic processing functionality into the existing SIMD processing pipeline. By combining cryptographic operations with the general-purpose SIMD execution flow, the system leverages the already-integrated interrupt handling and task management mechanisms of the main processor, eliminating the need for separate integration pathways
4Device complexity
If large state data is manipulated with general purpose registers, then device complexity is reduced, but the number of instructions and execution time increase
Solution Approach 1:
The SIMD register file is configured to accept and manipulate unusually long operand values (e.g., 128-bit, 256-bit, or 512-bit values) that exceed traditional SIMD register widths. This parameter change allows single instructions to operate on the entire cryptographic state data in one operation rather than requiring multiple instructions to process smaller general-purpose registers sequentially
Solution Approach 2:
The invention transitions from processing data in traditional word-sized units (32-bit or 64-bit) to processing data in extended vector units within the SIMD register file. This dimensional change in data representation allows parallel manipulation of multiple state variables simultaneously, increasing processing throughput while maintaining simplicity in the underlying hardware
Data Source
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AI summary
A data processing system (2) includes a single instruction multiple data register file (12) and single instruction multiple processing circuitry (14). The single instruction multiple data processing circuitry (14) supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file (12). The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.