SIMD Shift Circuit Layout to Prevent Internal Bus Data Overlap

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Solution Overview

Problem

Existing shift operation circuits face challenges in reducing circuit size and preventing data overlap when executing SIMD operations, particularly in floating-point adders, where the increase in circuit scale is exacerbated by overlapping bit numbers across multiple shift circuits.

Innovation Solution

The proposed shift operation circuit employs a configuration with multiple shift circuits coupled to internal buses of varying bit widths, a shift control circuit to manage common and independent shift amounts, and a bit selecting circuit to output valid data without overlap, allowing for reduced circuit design complexity and size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple shift circuits are used to execute SIMD operations, then processing capability is improved, but circuit size increases due to overlapping bit numbers

Engineering Contradiction:
ImproveSIMD processing capabilityVSAvoidcircuit size
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent divides the shift operation into multiple independent shift circuits (first shift circuit, second shift circuit, third shift circuit) that process different segments of data in parallel. Each shift circuit handles a specific portion of the SIMD operation, allowing simultaneous execution without requiring all circuits to handle overlapping bit ranges, thus reducing total circuit size while maintaining processing capability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a control dimension by using a control circuit to dynamically select which shift circuits are active and what shift amounts they apply. This control layer allows the system to execute SIMD operations with 4 or more elements using only 3 physical shift circuits by reconfiguring their operation modes, effectively adding a temporal/control dimension to the spatial arrangement of circuits

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If shift amount signals are independently controlled for each shift circuit, then processing flexibility is improved, but control complexity increases

Engineering Contradiction:
Improveshift operation flexibilityVSAvoidcontrol circuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The control circuit is designed to perform multiple functions: it generates shift amounts for the first shift circuit, selectively enables/disables the second and third shift circuits, and dynamically configures their operation modes. This universal control mechanism provides full flexibility for SIMD operations with 2, 3, or 4 elements using a single control unit, avoiding the need for separate control circuits for each shift operation

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The control circuit dynamically reconfigures the operation of shift circuits based on the SIMD operation requirements. The second and third shift circuits can be selectively activated or deactivated, and their shift amounts can be dynamically adjusted, allowing the system to adapt to different SIMD widths (2, 3, or 4 elements) without hardware changes or increased control complexity

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10056906B1Shift operation circuit and shift operation method
Publication Date: 2018.08.21 FUJITSU LTD
  • US10056906B1 patent drawing
  • US10056906B1 patent drawing
  • US10056906B1 patent drawing

AI summary

A shift operation circuit includes: shift circuits respectively coupled internal buses whose bit numbers partially overlap, each shift circuit receiving one of sets of divided data obtained by dividing input data and one of shift amount signals and outputting the corresponding divided data to a range shifted based on a shift amount represented by the corresponding shift amount signal from a reference bit position in the corresponding internal bus; a shift control circuit configured to output, during a first mode, shift amount signals whose shift amounts are common to the shift circuits, and configured to convert, during a second mode, a shift amount signal for each shift circuit, into a shift amount signal representing a shift range whose bit numbers do not overlap in the internal buses; and a bit selecting circuit configured to select valid divided data from bits whose bit numbers overlap in the internal buses.