SIMD SM3 Hashing Instructions for Microprocessor Pipeline Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current hardware implementations of cryptographic hash functions, such as SM3, face challenges in fitting into standard microprocessor execution pipelines due to latency and interrupt handling issues, and lack efficient data parallelism support, leading to performance bottlenecks.
Innovation Solution
The development of SIMD SM3 cryptographic hashing instructions and processing logic that enable SM3 message expansion and hash rounds to be performed in slices of iterations concurrently within a standard execution pipeline, leveraging SIMD vector registers to improve throughput and pipeline efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If straightforward hardware implementations (lookup memories, truth tables, FPGAs) are used for SM3 cryptographic hashing, then calculation speed is improved, but circuit area increases significantly
Solution Approach 1:
The patent segments the SM3 hashing algorithm into distinct functional components (message expansion, hash rounds, permutation operations) that can be independently implemented and optimized. This allows selective hardware acceleration of critical path operations while keeping less demanding operations in software, reducing overall circuit area while maintaining speed.
Solution Approach 2:
The patent transitions from traditional hardware implementation to a hybrid software-hardware approach using SIMD vector instructions. This dimensional shift allows parallel processing of multiple data elements simultaneously through vector registers, achieving high speed without proportionally increasing circuit area, as the parallelism is achieved through instruction-level parallelism rather than purely spatial parallelism.
2Speed
If complete hardware approach is used for cryptographic hashing, then calculation speed is improved, but integration into standard microprocessor execution pipeline becomes difficult
Solution Approach 1:
The patent creates a universal interface between the hashing operation and the microprocessor pipeline by implementing SM3 as SIMD vector instructions. This allows the hashing function to be integrated into the standard execution pipeline while maintaining the ability to process multiple data elements in parallel, achieving both speed and adaptability.
Solution Approach 2:
The patent introduces dynamic control mechanisms that allow the hashing operation to adapt to the microprocessor pipeline's timing and scheduling requirements. The SIMD instructions can be dynamically scheduled and executed alongside other instructions, enabling seamless integration into the standard execution pipeline while maintaining high performance.
3Reliability
If traditional hardware implementations are used, then cryptographic security is maintained, but data parallelism support is lacking leading to performance bottlenecks
Solution Approach 1:
The patent segments the hashing operation into independent parallelizable units that can be simultaneously executed on multiple data elements. Each SIMD lane independently processes a portion of the input data through the complete SM3 algorithm, maintaining cryptographic security while achieving high throughput through data-level parallelism.
Solution Approach 2:
The patent merges multiple independent hashing operations into a single SIMD instruction that processes multiple data elements simultaneously. This combining of parallel operations maintains the cryptographic security of each individual hash while dramatically increasing overall processing throughput through efficient utilization of vector processing units.
Data Source
AI summary
Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3 message expansions, from the first and second source data operand sets, determined by the specified expansion extent and store the result into a SIMD destination register. Some embodiments also execute instructions for a SIMD SM3 hash round-slice portion of the hashing algorithm, from an intermediate hash value input, a source data set, and a round constant set. Processor execution units perform a set of SM3 hashing round iterations upon the source data set, applying the intermediate hash value input and the round constant set, and store a new hash value result in a SIMD destination register.