SIMD Thread Divergence Handling via Active Mask Segmentation
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Solution Overview
Problem
Conventional SIMD architectures are limited in handling thread divergence and synchronization, which restricts the use of conditional break and return instructions, leading to inefficiencies in processing due to the need to disable threads that have not completed processing earlier than others.
Innovation Solution
The system breaks threads into SIMD thread groups based on an active mask, allowing independent traversal of branches and using control instructions to manage divergent threads through an execution stack, enabling conditional return and break instructions by disabling idle threads, thus maintaining efficient parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional SIMD architectures execute the same instruction synchronously for all threads, then processing efficiency is improved, but thread divergence handling is limited and conditional break/return instructions are restricted
Solution Approach 1:
The patent segments threads into multiple SIMD thread groups, where each group can independently handle branch execution. This allows different thread groups to traverse branches independently while maintaining SIMD efficiency within each group, resolving the contradiction between synchronous processing and thread divergence handling.
Solution Approach 2:
The patent dynamically manages thread activation using active masks and disable masks, allowing threads to be selectively enabled or disabled based on branch outcomes. This dynamic control enables conditional break and return instructions while maintaining efficient SIMD processing for active threads.
2Productivity
If threads are disabled while waiting for events in SIMD architecture, then parallel processing is maintained, but performance degradation occurs due to idle threads
Solution Approach 1:
The patent ensures continuous useful action by having threads that have completed processing wait for synchronization events rather than being completely disabled. The active mask mechanism allows completed threads to remain in the processing pipeline and resume execution when synchronization conditions are met, minimizing performance loss.
Solution Approach 2:
Threads automatically manage their own execution state through the active mask and disable mask mechanisms. When a thread completes processing earlier than others, it self-manages its waiting state and automatically resumes when synchronization is needed, reducing the need for external control overhead.
3Adaptability or versatility
If conditional break and return instructions are implemented with full thread independence, then control flow flexibility is improved, but SIMD parallelism is lost
Solution Approach 1:
By segmenting threads into SIMD thread groups, the patent allows conditional break and return instructions to be implemented at the group level rather than individual thread level. This maintains SIMD parallelism within each group while providing control flow flexibility between groups through the active mask mechanism.
Solution Approach 2:
The patent merges MIMD control flow flexibility with SIMD execution efficiency by allowing control instructions to operate on groups of threads simultaneously. The active mask mechanism combines the control flow capabilities of MIMD with the parallel execution efficiency of SIMD, achieving both goals.
Data Source
AI summary
One embodiment of a computing system configured to manage divergent threads in a SIMD thread group includes a stack configured to store state information for processing control instructions. A parallel processing unit is configured to perform the steps of determining if one or more threads diverge during execution of a conditional control instruction. A disable mask allows for the use of conditional return and break instructions in a multithreaded SIMD architecture. Additional control instructions are used to set up thread processing target addresses for synchronization, breaks, and returns.