SIMD Uniform Register Execution to Eliminate Redundant AI Computation
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Solution Overview
Problem
Existing artificial intelligence chips face performance issues due to redundant computation operations, particularly in Single Instruction Multiple Data (SIMD) execution, leading to inefficient use of computation resources and limited chip performance improvement.
Innovation Solution
An instruction execution apparatus and method that dispatches instructions as uniform instructions to a first computing unit for execution, where the uniform computation operations are performed and results are written into available uniform registers, reducing redundant operations and improving chip performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SIMD execution is used in artificial intelligence chips, then parallel processing capability is improved, but redundant computation operations occur leading to reduced execution efficiency
Solution Approach 1:
The patent extracts and identifies uniform computation operations from SIMD instruction streams using a detection unit. When redundant operations are detected, only one execution is performed and the result is broadcast to multiple destination registers, thereby removing the redundant computation steps while preserving the parallel processing capability.
Solution Approach 2:
The patent changes the execution parameter of SIMD instructions by introducing a uniform operation detection mechanism. When uniform operations are detected, the execution count parameter is effectively reduced from N (number of lanes) to 1, with the result being replicated to multiple registers, thus changing the computational parameter from full parallel execution to selective execution.
2Power
If more computing units are added to improve chip performance, then processing power is improved, but chip area increases
Solution Approach 1:
The patent makes existing computing units multi-functional by enabling them to handle both uniform and non-uniform computation operations. The same computing unit can execute SIMD instructions with uniform operations (where results are identical across lanes) without requiring dedicated hardware, thus improving chip performance without proportionally increasing chip area.
Solution Approach 2:
The detection unit automatically identifies uniform computation operations and manages the execution and result distribution without requiring additional computing resources. The system self-optimizes by detecting redundant operations and eliminating them, allowing existing hardware to serve multiple purposes efficiently.
Data Source
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AI summary
The present disclosure provides an instruction execution apparatus, which relates to a field of artificial intelligence technology, and in particular to a field of chip technology and a field of Single Instruction Multiple Data technology. A specific implementation solution includes: a dispatch unit configured to, in response to determining that at least one source register for an instruction to be executed corresponds to at least one of a plurality of uniform registers, dispatch the instruction to be executed as a uniform instruction to a first computing unit, where the uniform instruction includes a plurality of uniform computation operations; and the first computing unit configured to execute the uniform computation operations to obtain a uniform computation result, where the uniform computation result is written into at least one available uniform register among the plurality of uniform registers. The present disclosure further provides an instruction execution method, an electronic device, and a storage medium.