Adjacent SIMD Unit Reuse for Wide Result Generation
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Solution Overview
Problem
Conventional data processing systems face inefficiencies in handling wider results generated by SIMD instructions due to limited result bus sizes, leading to reduced throughput and increased latency, as they often require multiple instructions and cycles to process these results, which increases workload and complexity.
Innovation Solution
The system employs a single transaction model where unused adjacent SIMD execution units are utilized to send and combine results, allowing for wider results to be generated in a single cycle without the need for additional wiring or logic, thereby enhancing throughput and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional result buses are used for SIMD instructions, then the system structure remains simple, but the throughput decreases and latency increases when handling wider results
Solution Approach 1:
The patent makes adjacent SIMD execution units serve dual purposes: they execute instructions normally but also function as additional result output channels when needed. This allows the same hardware resources to handle both instruction execution and wider result generation, eliminating the need for dedicated wider result buses while maintaining high throughput and low latency.
Solution Approach 2:
The system uses its own existing SIMD execution units to generate wider results without requiring external or dedicated wider result buses. The unused execution units serve themselves by providing result output capability, turning idle resources into functional result channels and improving efficiency.
2Adaptability or versatility
If larger result buses are implemented to handle wider results, then the data width capability increases, but the device complexity and wiring requirements increase
Solution Approach 1:
Existing SIMD execution units are made multi-functional by allowing them to output results in addition to their primary instruction execution role. This eliminates the need for separate wider result buses, maintaining data width capability while avoiding increased wiring complexity.
Solution Approach 2:
The patent merges the result output function with the existing SIMD execution units rather than creating separate result buses. By combining result generation and transmission capabilities into the same units that execute instructions, the system achieves wider data width support without additional wiring infrastructure.
3Reliability
If multiple instructions and cycles are used to process wider results, then the result accuracy is maintained, but the workload and processing complexity increase
Solution Approach 1:
The system prepares wider result paths in advance by having adjacent SIMD execution units ready to receive and forward results. This preliminary setup allows wider results to be generated in a single cycle without requiring multiple processing steps or complex multi-cycle operations, maintaining accuracy while reducing processing complexity.
Solution Approach 2:
The patent enables continuous single-cycle generation of wider results by keeping adjacent SIMD execution units actively engaged in result transmission. This eliminates gaps or additional cycles that would otherwise be needed to process wider results, maintaining both accuracy and operational simplicity through continuous useful action.
Data Source
AI summary
A system for processing instructions with extended results includes a first instruction execution unit having a first result bus for execution of processor instructions. The system further includes a second instruction execution unit having a second result bus for execution of processor instructions. The first instruction execution unit is configured to selectively send a portion of results calculated by the first instruction execution unit to the second instruction execution unit during prosecution of a processor instruction if the second instruction execution unit is not used for executing the processor instruction and if the received processor instruction produces a result having a data width greater than the width of the first result bus. The second instruction execution unit is configured to receive the portion of results calculated by the first instruction execution unit and put the received results on the second results bus.