Reconfigurable SIMD Vector Processing Circuit for Dynamic Bit-Width Adaptation
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Solution Overview
Problem
Modern multimedia applications pose significant performance and power challenges for mobile computing devices due to varying requirements for operand bit-widths and degrees of parallelism, which existing SIMD architectures struggle to efficiently address.
Innovation Solution
A reconfigurable SIMD vector processing circuit with N×N bit multipliers and an adder block that can operate in different modes, allowing for flexible bit-width and parallelism configurations by using redundant formats and a compressor to generate and resolve products, thereby conserving die area and power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a SIMD architecture includes a separate configuration of multipliers and adders for each application requirement, then the architecture can meet different operand bit-widths and degrees of parallelism, but the device complexity and die area increase significantly
Solution Approach 1:
The patent implements a universal SIMD datapath that can be dynamically reconfigured to handle different operand bit-widths (e.g., 8-bit, 16-bit, 32-bit) and degrees of parallelism through a single shared configuration of multipliers and adders. The control logic dynamically adjusts the operation mode based on application requirements, eliminating the need for multiple separate hardware configurations while maintaining full adaptability.
Solution Approach 2:
The patent introduces dynamic reconfiguration capability where the SIMD architecture can change its operational parameters (bit-width, parallelism degree) at runtime through control signals. The multipliers and adders can be dynamically allocated and configured based on the specific application needs, allowing the system to adapt from 8-bit operations to 32-bit operations and adjust parallelism levels without hardware changes.
2Adaptability or versatility
If multiple separate SIMD datapaths are provided for different applications, then all application requirements can be met, but the power consumption increases due to having multiple active configurations
Solution Approach 1:
A single shared SIMD datapath is designed to serve multiple applications through dynamic reconfiguration. The same multipliers and adders are reused across different applications by changing control parameters, ensuring that only one configuration is active at a time and consuming power efficiently, while still supporting diverse application requirements.
Solution Approach 2:
The control logic automatically determines the appropriate configuration mode based on the application requirements and dynamically adjusts the SIMD datapath parameters without requiring external intervention. This self-service mechanism ensures optimal power usage by activating only the necessary computational resources for each specific application scenario.
3Device complexity
If a fixed configuration of multipliers and adders is used, then the device complexity is reduced, but the architecture cannot efficiently handle varying operand bit-widths and parallelism requirements
Solution Approach 1:
The patent implements a dynamically reconfigurable SIMD architecture where a single fixed physical configuration of multipliers and adders can assume multiple logical configurations through control signals. The hardware structure remains fixed and simple, but its operational characteristics (bit-width, parallelism degree) are dynamically adjustable to match application requirements, achieving both simplicity and flexibility.
4Productivity
If separate SIMD datapaths are implemented for different applications, then application-specific performance is optimized, but the die area occupied by the processing circuit increases
Solution Approach 1:
The patent designs a universal SIMD datapath that can be dynamically configured to optimize performance for different applications using the same hardware resources. The single shared configuration of multipliers and adders can be adapted through control logic to deliver application-specific performance optimization without requiring separate dedicated hardware for each application, thereby conserving valuable die area.
Data Source
AI summary
A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.