SIMD Processing Module Vector Subdivision for Parallel Execution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing SIMD processing modules are limited by the fixed width of their vector processing units, which restricts the flexibility to execute instructions on varying vector widths, leading to suboptimal utilization of wider units and inefficient parallel processing.
Innovation Solution
A SIMD processing module comprising multiple vector processing units that can execute instructions on subvectors of a vector in parallel, allowing instructions written for a specific width to be executed on more data items by distributing the workload across multiple units, each starting at different positions within the vector.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a wider vector processing unit is used, then the number of data items processed in parallel increases, but the chip area and manufacturing cost increase
Solution Approach 1:
The patent divides a wide vector processing unit into multiple narrower vector processing units (e.g., two 4-way VPUs instead of one 8-way VPU). Each narrower unit processes a subset of the data items, and their results are combined to achieve the same overall throughput as a wider unit would provide, thereby reducing the chip area required while maintaining processing capacity.
2Productivity
If a wider vector processing unit is used, then fewer execution cycles are needed, but routing complexity increases due to more ways needing access to registers
Solution Approach 1:
The patent segments the vector processing functionality into multiple narrower VPUUs, each with its own register file. This segmentation reduces routing complexity because each narrower unit has fewer ways that need to access registers simultaneously, simplifying the interconnect architecture while maintaining overall processing throughput through parallel execution of multiple narrower units.
3Productivity
If instructions are written for a specific vector width, then execution efficiency is optimized, but adaptability to different vector widths is reduced
Solution Approach 1:
The patent creates a universal execution environment where instructions compiled for a specific vector width can be executed on multiple narrower vector processing units. The system is designed to handle instructions with vector length indicators that specify the intended width, allowing the same instruction to be efficiently executed whether the target architecture uses 4-way, 8-way, or other width VPUs, thereby providing both optimization and adaptability.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A SIMD processing module is provided, comprising multiple vector processing units ("VUs"), which can be used to execute an instruction on respective parts (or "subvectors") within a vector. A control unit determines a vector position indication for each of the VUs to indicate which part of the vector that VU is to execute the instruction on. Therefore, the vector is conceptually divided into subvectors with the respective VUs executing the instruction on the respective subvectors in parallel. Each VU can then execute the instruction as intended, but only on a subsection of the whole vector. This allows an instruction that is written for execution on an n-way VU to be executed by multiple n-way VUs, each starting at different points of the vector, such that the instruction can be executed on more than n of the data items of the vector in parallel.