SIMD Processor Video Analytics Bit Expansion Prevention

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Solution Overview

Problem

Conventional video analytics methods are inefficient for embedded applications due to high processing demands from filtering operations, which require large amounts of processing resources and are ill-suited for network cameras, and general-purpose processors with Single Instruction, Single Data (SISD) architecture perform poorly in video analytics tasks.

Innovation Solution

A SIMD processor with a rich array of instructions, including a splice and doubled absolute value instruction, is used to efficiently implement video analytics filters that maintain the number of pixel bits constant throughout operations, allowing for simultaneous processing of multiple pixels without bit expansion, thereby avoiding processor bottlenecks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional filtering operations are used in video analytics, then accurate results are achieved, but processing resources are excessively consumed and processing capacity is halved

Engineering Contradiction:
Improvefiltering accuracyVSAvoidprocessing capacity
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent changes the bit-width parameter from 16-bit conventional filtering to 8-bit filtering, reducing the data size by half while maintaining acceptable accuracy for video analytics applications. This parameter change directly addresses the contradiction by reducing processing capacity requirements while preserving sufficient filtering accuracy for motion detection and video analysis tasks.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If general-purpose SISD processors are used for video analytics, then device complexity is reduced, but processing performance is inherently poor due to single-pixel processing

Engineering Contradiction:
Improveprocessor architectureVSAvoidvideo analytics performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent merges multiple pixel processing operations into a single SIMD instruction cycle, allowing simultaneous processing of multiple pixels (e.g., 4 pixels in a 32-bit register) while maintaining relative simplicity of implementation on standard processors. This merging approach resolves the contradiction by dramatically improving processing performance without requiring complex custom hardware architectures.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from processing pixels sequentially in time (SISD) to processing multiple pixels in parallel space (SIMD), effectively adding a spatial dimension to the processing architecture. This dimensional change enables simultaneous multi-pixel operations while keeping the processor design relatively simple, resolving the performance-complexity contradiction.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Measurement precision

If 16-bit filtering is used to maintain accurate results, then measurement precision is improved, but the number of bits required doubles compared to input pixels

Engineering Contradiction:
Improvefiltering result accuracyVSAvoidbit width
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent changes the bit-width parameter from 16-bit to 8-bit throughout the filtering operation, preventing bit expansion. By maintaining consistent 8-bit width from input through processing to output, the patent reduces the quantity of data by half while accepting that some precision is sacrificed for the sake of efficiency in embedded video analytics applications.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8401327B2Apparatus, computer program product and associated methodology for video analytics
Publication Date: 2013.03.19 AXIS
  • US8401327B2 patent drawing
  • US8401327B2 patent drawing
  • US8401327B2 patent drawing

AI summary

A processor and associated methodology employ a SIMD architecture and instruction set to efficiently perform video analytics operation on images. The processor contains a group of SIMD instructions used by the method to implement video analytic filters that avoid bit expansion of the pixels to be filtered. The filters hold the number of bits representing a pixel constant throughout the entire operation, conserving processor capacity and throughput when performing video analytics.