SIMD Walk Instructions for Graph Streaming Processors

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Graph streaming processors (GSPs) face performance issues due to their inability to handle certain SIMD widths, leading to slowed down operations and overall software performance.

Innovation Solution

The implementation of walk instructions and a walk/endwalk mechanism dynamically modifies the SIMD width, allowing the GSP to iterate and process SIMD threads at lower widths, optimizing hardware iteration and resource utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the GSP operates at higher SIMD widths beyond native hardware capability, then processing throughput is improved, but execution speed deteriorates significantly

Engineering Contradiction:
Improveprocessing throughputVSAvoidexecution speed
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The patent segments the SIMD processing into multiple iterations, where each iteration processes a subset of channels (walk size) that matches the native hardware capability. The thread arbiter divides the full SIMD thread into multiple walk iterations, each handling a manageable subset of channels, thereby maintaining execution speed while achieving overall high throughput through systematic segmentation of the processing workload.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic adjustment of the walk size parameter, allowing the system to adaptively optimize the number of channels processed per iteration based on hardware capabilities and workload characteristics. This dynamic parameter enables the GSP to flexibly balance between throughput and execution speed, adjusting the processing granularity in real-time to match native hardware performance optima.

Inventive Principle:
Principle #15Dynamics

2Quantity of substance

If the SIMD width exceeds native maximum width, then more data can be processed in parallel, but hardware iteration capability is compromised

Engineering Contradiction:
Improvedata processing capacityVSAvoidhardware iteration speed
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent segments the large SIMD width into multiple smaller subsets, where each subset (walk size) corresponds to the native maximum width capability. The thread arbiter iterates through these segmented subsets in multiple passes, ensuring that each iteration operates within native hardware limits while collectively processing the entire data set, thus preserving both data capacity and iteration productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent ensures continuous useful action by implementing an iterative mechanism that systematically processes each subset of channels without idle hardware cycles. The walk instruction continuously iterates through all channel subsets, maintaining full hardware utilization across multiple iterations, thereby achieving high productivity despite the need to process more data than native width allows.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If walk size is increased to process more channels per iteration, then throughput is improved, but register resource utilization increases

Engineering Contradiction:
ImprovethroughputVSAvoidregister resource utilization
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies partial action by processing only a subset of channels (walk size) in each iteration rather than all channels simultaneously. This partial processing approach achieves adequate throughput by systematically covering all channels across multiple iterations, while significantly reducing the register resource requirements compared to processing the full SIMD width in a single pass.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10996960B1Iterating single instruction, multiple-data (SIMD) instructions
Publication Date: 2021.05.04 BLAIZE INC
  • US10996960B1 patent drawing
  • US10996960B1 patent drawing
  • US10996960B1 patent drawing

AI summary

Methods, systems and apparatuses for performing walk operations of single instruction, multiple data (SIMD) instructions are disclosed. One method includes initiating, by a scheduler, a SIMD thread, where the scheduler is operative to schedule the SIMD thread. The method further includes fetching, a plurality of instructions for the SIMD thread. The method further includes determining, by a thread arbiter, at least one instruction that is a walk instruction, where the walk instruction iterates a block of instructions for a subset of channels of the SIMD thread, where the walk instruction includes a walk size, and where the walk size is a number of channels in the subset of channels of the SIMD thread that are processed in a walk iteration in association with the walk instruction. The method further includes executing the walk instruction based on the walk size.