Simple Cell Interconnection Reducing Wiring Complexity in ICs
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Solution Overview
Problem
The increasing complexity of wirings in integrated circuits (ICs) due to smaller device sizes and higher device integration leads to signal delay and limits performance improvement.
Innovation Solution
The implementation of a simple cell interconnection method in ICs, where cells are aligned with input and output pins on the same track, reducing the need for higher wiring layers and simplifying the layout by using a single pattern in the first conductive layer for connections between adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is decreased and device integration is increased, then the number of devices in IC is improved, but wiring complexity increases
Solution Approach 1:
The patent merges the wire and pin patterns into a single conductive layer pattern. The wire connecting adjacent cells is formed in the same first conductive layer as the input and output pins, allowing the wire pattern to be combined with the pin patterns to form a unified first pattern. This merging eliminates the need for separate wiring layers, thereby reducing wiring complexity while maintaining high device integration.
Solution Approach 2:
The first conductive layer serves multiple functions: it forms both the input and output pins of cells and the wires connecting adjacent cells. This multi-functionality of the first conductive layer reduces the total number of wiring layers needed, simplifying the overall wiring structure while supporting increased device integration.
2Quantity of substance
If device size is decreased and device integration is increased, then the number of devices in IC is improved, but signal delay increases
Solution Approach 1:
By merging the wire connection into the same conductive layer as the pins, the patent reduces the number of interlayer via connections needed. Signals can be transmitted within the first conductive layer without transitioning to higher wiring layers, reducing signal delay while supporting increased device integration.
Solution Approach 2:
The patent utilizes the planar dimension of the first conductive layer more effectively by extending wires in the first direction across cell boundaries. This approach keeps connections within the same layer rather than moving to higher layers, reducing vertical transitions and associated signal delays.
3Quantity of substance
If complex wiring is used to connect cells, then device integration is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent combines the wire formation process with the pin formation process in the same first conductive layer. This merging reduces the total number of patterning and deposition steps needed, simplifying the manufacturing process while maintaining high device integration.
Solution Approach 2:
The first conductive layer is designed to serve dual purposes: forming pins for individual cells and forming inter-cell wires. This universal approach reduces the number of separate manufacturing steps required, making the process easier to manufacture while achieving high device integration.
Data Source
AI summary
An integrated circuit (IC) includes: a first cell including an input pin and an output pin extending in a first direction; a second cell adjacent to the first cell in the first direction and including an input pin and an output pin extending in the first direction; a first cell isolation layer extending between the first cell and the second cell in a second direction crossing the first direction; and a first wire extending in the first direction, overlapping the first cell isolation layer, and being connected to the output pin of the first cell and the input pin of the second cell, wherein the output pin of the first cell, the input pin of the second cell, and the first wire are formed in a first conductive layer as a first pattern extending in the first direction.