Simple Linear Fast Adder With Finite-State Iteration
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Solution Overview
Problem
Existing adders, such as Ripple Carry Adders and Carry Look-Ahead adders, face issues with propagation delay and increased complexity as the number of bits increases, leading to inefficiencies in Central Processing Units (CPUs).
Innovation Solution
A fast adder based on a finite state machine with a novel axiomatization of mathematics, utilizing a small count of 'AND' and 'XOR' logic gates and four registers per bit, achieving linear growth and complexity, with logarithmic time delay and reduced material and energy costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If Carry Look-Ahead adder is used to reduce propagation delay, then addition speed is improved, but circuit area and complexity increase considerably
Solution Approach 1:
The adder is divided into modular 4-bit subunits that can be connected in series. Each subunit handles a specific bit position and uses the same standardized structure with registers and logic gates, allowing the n-bit adder to be constructed by repeating the 4-bit module while maintaining linear complexity growth
Solution Approach 2:
The adder uses a dynamic iterative process where results are computed in multiple time steps rather than a single parallel computation. The finite state machine transitions through states, updating partial sums and carry bits sequentially, which reduces the immediate computational complexity while maintaining speed through time-multiplexed operations
2Device complexity
If traditional adder algorithms are used, then implementation is simple, but propagation delay increases with more bits
Solution Approach 1:
The adder pre-computes and stores intermediate results in registers during iterative steps. By maintaining partial sums and carry bits in register files and updating them systematically through the finite state machine, the circuit prepares subsequent calculations in advance, reducing the overall propagation delay for large n-bit additions
Solution Approach 2:
The adder continuously updates and processes carry bits and partial sums through multiple clock cycles using the finite state machine. Rather than waiting for a single sequential carry propagation, the system continuously performs addition operations across different bit positions in overlapping time steps, maintaining productive computation throughout the process
3Speed
If parallel adder structure is used to reduce propagation delay, then addition speed is improved, but area and complexity increase
Solution Approach 1:
The adder architecture segments the n-bit addition task into multiple 4-bit subunits connected in series. Each subunit uses a standardized set of registers and logic gates, allowing the total area to grow linearly with n rather than requiring complex parallel structures that would scale quadratically or exponentially
Solution Approach 2:
The 4-bit subunit is designed as a universal module that can handle different bit positions and operations through the finite state machine's state transitions. The same basic structure with XOR gates, AND gates, and registers serves multiple functions across different computational steps, reducing the need for specialized hardware for each operation
Data Source
AI summary
Disclosed herein is a fast adder design based on a novel axiomatization of mathematics, of natural and real numbers, by the author. Addition is a Finite State Machine that, on an average, takes logon iterations to calculate a n-bit addition. Further, for the proposed fast adder, the probability of a n-bit addition taking k≤n iterations to complete, is equal to the probability of k consecutive heads in n fair coin tosses. The circuitry is linear and simple, in the sense that adding bits to the inputs does not complicate the circuit topology. The growth is linear, and the instruction set is constant, and hardware based.