SIMT Atomic Instruction Execution With Optimized Peeling Loops
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Solution Overview
Problem
Conventional SIMT processing architectures face inefficiencies due to unnecessary computational workload and increased power consumption from redundant memory accesses and false failures in peeling loops during atomic operations, particularly in scenarios where multiple threads attempt to access shared memory.
Innovation Solution
Optimized peeling loops that partition threads targeting the same memory location into sets, executing one thread per set while fast-failing others, and directly returning results to predicate registers, reducing redundant memory accesses and false failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional peeling loops are used to execute atomic instructions in SIMT architectures, then all threads in a set attempt to access shared memory locations, but this results in redundant memory accesses and increased power consumption
Solution Approach 1:
The patent segments the set of threads into different groups based on their memory access patterns. Threads are divided into those that will successfully access their target memory locations and those that will fail, allowing the system to handle each group differently and avoid redundant operations from threads destined to fail.
Solution Approach 2:
The patent performs preliminary actions by executing certain threads before others in a staged manner. Fast-failing threads are executed first to quickly determine their fate, and their results are used to prevent slower, non-fast-failing threads from performing redundant memory accesses, thereby reducing overall power consumption.
2Productivity
If conventional peeling loops execute atomic instructions for multiple threads, then all threads attempt memory access, but this causes redundant memory accesses and increased latency
Solution Approach 1:
The patent segments threads into fast-failing and non-fast-failing groups, allowing the system to process fast-failing threads separately and prevent them from causing delays for other threads. This segmentation enables parallel processing of different thread groups, improving overall throughput while reducing latency for successful operations.
Solution Approach 2:
The patent implements a mechanism where fast-failing threads are quickly identified and skipped over in terms of full memory access execution. The system rushes through the determination of fast-failing thread outcomes and uses this information to prevent other threads from performing unnecessary memory accesses, thereby reducing latency.
3Productivity
If peeling loops are used to handle atomic operations with thread partitioning, then some threads are fast-failed, but this creates false failures that reduce overall efficiency
Solution Approach 1:
The patent implements feedback mechanisms where the outcomes of fast-failing thread executions are captured and used to inform the execution of subsequent threads. This feedback allows the system to make informed decisions about which threads should proceed with full execution and which should be skipped, improving efficiency without creating false failures.
Data Source
AI summary
A first set of threads having a same address corresponding to the shared memory is identified from a group of active threads associated with an instruction to update a shared memory. A first thread of the first set of threads is selected. The instruction is executed for the first thread using the same address to access the shared memory. Attempts to execute the instruction for remaining threads of the first set of threads are delayed until after the first thread is executed and until at least one of the remaining threads of the first set of threads is not guaranteed to fail execution of the instruction.