SIMT Core Transactional Memory Conflict Resolution

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Solution Overview

Problem

GPU transactional memory systems face performance degradation due to increased concurrency leading to resource contention and conflicts, which existing systems like Kilo TM and Warp TM struggle to manage efficiently, resulting in decreased performance and increased power consumption.

Innovation Solution

Implementing early-abort global conflict resolution and pause-and-go execution schemes, where conflicts are resolved at the Single Instruction Multiple Threads (SIMT) cores, reducing contention at the commit units and interconnection network, and pausing transactions to prevent work loss from conflicts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If concurrency is increased to improve processing throughput, then productivity increases, but resource contention and conflicts increase leading to performance degradation

Engineering Contradiction:
Improveprocessing throughputVSAvoidtransaction correctness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system performs preliminary conflict detection during the execution phase by maintaining read and write sets for each transaction. This early detection mechanism identifies potential conflicts before the commit phase, allowing the system to abort conflicting transactions in advance and prevent performance degradation from repeated commit-phase conflicts.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary conflict detection mechanism that mediates between multiple concurrent transactions. The read and write sets act as intermediaries to track and detect conflicts between transactions, enabling the system to manage high concurrency while maintaining correctness by identifying and resolving conflicts before they affect transaction commits.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If conflict detection is performed during execution (eager detection), then conflicts are identified early, but system complexity and overhead increase

Engineering Contradiction:
Improveconflict detection timeVSAvoidtransaction management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The conflict detection process is segmented into two distinct phases: execution phase and commit phase. During execution, the system maintains read and write sets without performing full conflict detection. Actual conflict detection is performed during the commit phase by comparing the committing transaction's read set against other transactions' write sets. This segmentation reduces execution-phase overhead while still providing timely conflict detection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs partial conflict detection by maintaining only read and write sets during execution, rather than performing complete conflict detection at all times. Full conflict detection is performed selectively during the commit phase when necessary, reducing overall system complexity and overhead while still achieving effective conflict management.

Inventive Principle:
Principle #16Partial or excessive action

3Device complexity

If conflict detection is performed at commit stage (lazy detection), then execution overhead is reduced, but conflicts are detected later causing more aborts

Engineering Contradiction:
Improveexecution overheadVSAvoidtransaction commit rate
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The system performs preliminary preparation during execution by maintaining read and write sets, which are then used for efficient conflict detection at commit time. This preliminary action reduces the complexity of commit-phase detection while enabling timely conflict identification, improving both execution efficiency and commit success rate.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses feedback from the maintained read and write sets to enable rapid conflict detection during the commit phase. The feedback mechanism allows the system to quickly determine whether a committing transaction conflicts with other transactions, improving commit-phase efficiency and reducing the number of unsuccessful commit attempts.

Inventive Principle:
Principle #23Feedback

4Device complexity

If versioning meta-data is stored on memory side (ownership records), then commit validation is simplified, but memory bandwidth consumption increases

Engineering Contradiction:
Improvecommit validation complexityVSAvoidmemory bandwidth usage
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The system extracts the versioning meta-data (read and write sets) from the memory side and stores it on the processor side during transaction execution. This extraction reduces memory bandwidth consumption by avoiding continuous memory accesses for version tracking, while the extracted data is then used for efficient conflict detection during the commit phase.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The read and write sets serve as intermediary structures that store versioning information locally on the processor side. These intermediaries eliminate the need for continuous memory accesses to track version changes, reducing memory bandwidth usage while still enabling effective conflict detection and commit validation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10664286B2Enhanced performance for graphical processing unit transactional memory
Publication Date: 2020.05.26 BOARD OF SUPERVISORS OF LOUISIANA STATE UNIV & AGRI & MECHANICAL COLLEGE
  • US10664286B2 patent drawing
  • US10664286B2 patent drawing
  • US10664286B2 patent drawing

AI summary

A computer system implementing transactional memory. The computing system includes a plurality of Single Instruction Multiple Thread (SIMT) cores and a conflicting address table (CAT) for each core. The CAT stores word addresses for reads and writes correlated with flags indicating whether a corresponding word is written or read by a committing transaction. The CATs for the different SIMT cores are coupled together by an interconnect. A commit unit (CU) is coupled to the SIMT cores and is configured to validate transactions. The cores access its CAT to access a first address of data affected by a first transaction to be committed at the CU. The first address is compared to a second address affected by a second transaction. When the first address matches the second address, the core delays or prevents committing the first transaction at the CU by pausing the first transaction or aborting the first transaction.