Runtime Memory Bank Mapping for SIMT Bank Conflict Reduction
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Solution Overview
Problem
Existing graphics processing units (GPUs) and single instruction, multiple thread (SIMT) processors face inefficiencies in mapping memory addresses to memory banks, leading to suboptimal performance in graphics and general-purpose computing tasks.
Innovation Solution
The proposed solution involves dynamically reconfiguring memory address mapping to memory banks during runtime, utilizing banked memory access circuitry and address masks to optimize memory access for GPUs and SIMT processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory addresses are mapped to memory banks using a fixed mapping scheme, then the hardware structure is simple, but memory access efficiency deteriorates due to bank conflicts and suboptimal performance
Solution Approach 1:
The patent implements dynamic memory address mapping by introducing reconfigurable logic that can change the mapping scheme between different memory banks at runtime. Instead of a fixed mapping, the system dynamically selects and applies different mapping functions (e.g., different address mask configurations) based on the current computational workload and access patterns, thereby optimizing memory access efficiency without permanently increasing hardware complexity.
Solution Approach 2:
The patent changes the parameters of the memory mapping function by introducing configurable address masks and offset values that can be adjusted at runtime. By modifying these parameters dynamically, the system adapts the mapping scheme to match different data access patterns, resolving bank conflicts and improving memory access efficiency without requiring a complete redesign of the memory architecture.
2Productivity
If dynamic reconfiguration of memory mapping is implemented, then memory access efficiency is improved, but hardware complexity increases
Solution Approach 1:
The patent segments the memory address mapping function into separate configurable components, such as individual address masks for different bank groups and offset selectors. This segmentation allows the system to apply reconfiguration only where needed rather than globally, reducing the overall complexity overhead while still achieving performance optimization in critical memory access paths.
Solution Approach 2:
The patent designs a universal reconfiguration mechanism that can serve multiple functions: it can adapt to different data access patterns, resolve various types of bank conflicts, and optimize performance for different computational workloads. This multi-functional approach consolidates what would otherwise require multiple specialized components, thereby improving performance without proportionally increasing hardware complexity.
3Productivity
If banked memory access circuitry is used, then memory bandwidth is increased, but access patterns become more complex leading to suboptimal utilization
Solution Approach 1:
The patent introduces an intermediary layer (the reconfigurable mapping logic) between the processor and the banked memory array. This intermediary automatically handles the complexity of optimizing access patterns by dynamically selecting appropriate mapping schemes, thereby maintaining high memory bandwidth utilization while shielding the processor from the complexity of direct memory access pattern management.
Solution Approach 2:
The patent implements self-service memory optimization where the reconfigurable mapping logic automatically adapts to the current workload characteristics and optimizes its own configuration without external intervention. The system monitors access patterns and autonomously adjusts the mapping parameters to maintain optimal performance, reducing the operational burden on software while preserving high bandwidth utilization.
Data Source
AI summary
A processor of an aspect includes a banked memory. The banked memory has a plurality of memory banks. The processor also includes a single instruction, multiple thread (SIMT) processor. The SIMT processor includes a plurality of processor elements. The processor elements are to perform memory access operations with memory addresses. The processor also includes banked memory access circuitry coupled with the banked memory, and coupled with the SIMT processor. The banked memory access circuitry is to access data in the banked memory with each of the memory addresses. The banked memory access circuitry is reconfigurable during runtime to map the memory addresses to the memory banks in a plurality of different ways. Other processors, methods, systems, and non-transitory machine-readable storage mediums are also disclosed.