SIMT Processor Scheduling Circuitry Runner-Up Execution Position

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Solution Overview

Problem

Scheduling in single instruction multiple thread (SIMT) processors is inefficient due to the lack of calculation of a runner-up execution position, leading to increased computational workload and potential inefficiencies in memory access and branch prediction.

Innovation Solution

Incorporating scheduling circuitry that calculates both the next scheduled execution position and a runner-up execution position, allowing for simplified scheduling between these points, reducing energy consumption and improving efficiency by incrementing execution positions and reusing shared determination hardware.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a runner-up execution position is calculated in addition to the next scheduled execution position, then scheduling efficiency is improved and energy consumption is reduced, but computational workload increases

Engineering Contradiction:

Improvescheduling efficiencyVSAvoidcomputational workload

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The runner-up execution position is calculated in advance during the same hardware cycle as the next scheduled execution position. This preliminary calculation allows the system to prepare alternative execution positions before they are needed, enabling faster scheduling decisions without requiring additional full determination cycles later.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The scheduling system creates a copy of the determination hardware logic to simultaneously compute both the next scheduled execution position and the runner-up execution position. This copying approach allows both positions to be determined in parallel during the same hardware cycle, avoiding the need for sequential processing that would increase overall computational workload.

Inventive Principle:

Principle #26Copying

2Measurement precision

If full determination of scheduling is performed frequently, then scheduling accuracy is improved, but energy consumption increases

Engineering Contradiction:

Improvescheduling accuracyVSAvoidenergy consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The system performs a simplified scheduling determination using only the runner-up execution position for cases where threads are executing sequentially without complex branching. This partial determination approach handles the majority of scheduling scenarios with reduced computational effort, reserving full determination only for cases involving branch points or re-convergence points.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

Different scheduling determination strategies are applied to different regions of the execution flow. Full determination with both next scheduled and runner-up positions is performed at critical points (branch points, re-convergence points), while simplified incrementing is used in regular sequential execution regions. This local differentiation optimizes the balance between accuracy and energy consumption.

Inventive Principle:

Principle #3Local quality

3Device complexity

If shared determination hardware is used to determine both positions, then device complexity is reduced, but calculation time may increase

Engineering Contradiction:

Improvehardware structureVSAvoidcalculation time

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The shared determination hardware alternates between determining the next scheduled execution position and the runner-up execution position in a periodic manner. During each determination cycle, the hardware first computes the next scheduled position, then uses the same hardware to compute the runner-up position in the subsequent phase of the same cycle, achieving both goals without requiring permanently duplicated hardware.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS9436473B2Scheduling program instructions with a runner-up execution position

Publication Date: 2016.09.06 ARM LTD

AI summary

A single instruction multiple thread (SIMT) processor includes scheduling circuitry for calculating a next scheduled execution point for execution circuits which execute respective threads corresponding to a common program. In addition to calculating the next scheduled execution point, the scheduling circuitry determines a runner up execution point which would have been determined as the next scheduled execution point if the threads which actually correspond to the next scheduled execution point had been removed from consideration. This runner up execution point is used to identify points of re-convergence within the program flow and as part of the operation of a static branch predictor.