Simulated Annealing Integerization of Hidden Weights for IoT Edge Intelligence
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Solution Overview
Problem
Highly parameterized deep neural networks (NNs) pose significant computational and memory requirements, making them resource-intensive and costly, which is disadvantageous for resource-constrained devices and applications, and specialized NN-specific chips are complex and costly to manufacture.
Innovation Solution
The use of simulated annealing-based neural network optimization methodologies to fine-tune neuron weights in hidden layers of multilayer perceptron hardware, resulting in an energy-efficient, lightweight, and compressed neural network model, which reduces the number of circuit gates and power demands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If highly parameterized deep neural networks are used to achieve accurate models, then prediction accuracy is improved, but computational cost and memory requirements increase significantly
Solution Approach 1:
The patent applies parameter changes by converting continuous neuron weights to discrete integer values through a simulated annealing-based quantization process. This transforms the weight parameters from high-precision floating-point numbers to lower-precision integers, reducing computational complexity and memory requirements while maintaining acceptable prediction accuracy for resource-constrained IoT devices
2Measurement precision
If highly parameterized deep neural networks are used to achieve accurate models, then prediction accuracy is improved, but memory requirements increase significantly
Solution Approach 1:
The patent reduces memory requirements by changing the parameter representation from floating-point to integer format. The simulated annealing quantization process converts weight matrices to discrete integer values, significantly reducing the storage memory needed while preserving the essential predictive capabilities of the neural network for edge intelligence applications
3Productivity
If specialized NN-specific chips are used to process neural network models efficiently, then processing efficiency is improved, but manufacturing cost and power demands increase
Solution Approach 1:
The patent adopts a software-based optimization approach rather than hardware specialization. By using simulated annealing quantization to optimize neural network models for general-purpose processors, the solution avoids the high manufacturing costs and power demands of specialized NN chips while maintaining acceptable processing efficiency for resource-constrained applications
Solution Approach 2:
The patent changes the computational parameters from floating-point operations to integer operations, enabling efficient execution on general-purpose processors without requiring specialized hardware. This parameter transformation allows standard processors to handle neural network inference with reduced power consumption and manufacturing cost
4Measurement precision
If larger neural network models are used to improve accuracy, then predictive performance is improved, but run time increases
Solution Approach 1:
The patent applies parameter changes by quantizing weights to integers and optimizing the network structure through simulated annealing. This reduces the computational burden of large models by enabling faster integer arithmetic operations and potential model compression, thereby reducing inference run time while maintaining predictive performance on resource-constrained devices
Data Source
AI summary
Methods and systems for hardware optimization of a neural network model are disclosed. The methods and systems include: obtaining a trained neural network model, the trained neural network model comprising a plurality of neurons, the plurality of neurons comprising a plurality of neuron layers and a plurality of neuron weights; performing a simulated annealing process for the plurality of neuron weights; generate a plurality of new weights for one of the plurality of neuron layers; retrain the trained neural network model using the plurality of new weights; obtaining an updated plurality of neuron weights; obtaining an optimized neural network model using the updated plurality of neuron weights; and generating an optimized circuit layout for hardware that implements the optimized neural network model obtained using the updated plurality of neuron weights. Other aspects, embodiments, and features are also claimed and described.