Simulated Annealing Memory Allocation for Spatial Arrays

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Solution Overview

Problem

Existing memory allocation systems face challenges in balancing memory access points, leading to increased latency due to resource contention and inefficient designs that only consider single factors, such as issue counts, resulting in suboptimal execution times.

Innovation Solution

The implementation of a spatial array with a configurable architecture and simulated-annealing process to intelligently assign memory operations across multiple memory controllers, optimizing memory allocation based on multiple cost functions to reduce latency and enhance performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If global resource allocation is implemented, then resource distribution is achieved, but it becomes difficult to fairly balance and modify once implemented

Engineering Contradiction:
Improvemodifiability of resource allocationVSAvoidcomplexity of global resource allocation system
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic resource allocation where the system can adaptively reassign memory operations to memory controllers based on current workload conditions. The allocation is not fixed but can be modified through feedback mechanisms that monitor contention and performance, allowing the system to evolve from static to dynamic management while maintaining fairness across multiple controllers.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system employs feedback loops that monitor memory access patterns, contention levels, and performance metrics. This feedback information is used to continuously optimize the allocation of memory operations across controllers, enabling fair balancing without requiring complex manual reconfiguration. The feedback mechanism allows automatic adaptation to changing conditions.

Inventive Principle:
Principle #23Feedback

2Productivity

If memory allocation considers only one factor (e.g., issue counts), then allocation is simple, but execution time is lost due to contention

Engineering Contradiction:
Improveexecution time efficiencyVSAvoidcomplexity of allocation criteria
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent transitions from single-parameter allocation (issue counts only) to multi-parameter allocation that considers multiple factors including contention levels, memory controller load, access patterns, and performance metrics. This change in allocation parameters enables the system to optimize execution time by distributing operations based on a comprehensive set of criteria rather than a single metric.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The allocation strategy combines multiple evaluation criteria into a composite allocation decision framework. Rather than relying on a single factor, the system integrates multiple parameters (contention, load, patterns) into a unified allocation mechanism that produces superior execution performance while managing the complexity through structured composite evaluation.

Inventive Principle:
Principle #40Composite materials

3Loss of time

If memory operations are concentrated on fewer controllers, then allocation is simpler, but resource contention increases and latency increases

Engineering Contradiction:
Improvememory latencyVSAvoidcomplexity of distribution management
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent segments memory operations and distributes them across multiple memory controllers rather than concentrating them on fewer controllers. This segmentation reduces contention at individual controllers and lowers memory latency by parallelizing access across the distributed controller architecture, while management complexity is handled through automated allocation algorithms.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11249683B2Simulated-annealing based memory allocations
Publication Date: 2022.02.15 INTEL CORP
  • US11249683B2 patent drawing
  • US11249683B2 patent drawing
  • US11249683B2 patent drawing

AI summary

Systems, apparatuses and methods may provide for technology that determines a plurality of memory operations associated with a data-flow graph that represents a computer code, where a spatial architecture executes the data-flow graph and the spatial architecture includes a plurality of memory controllers, randomly assigns one or more of the plurality of memory operations to one or more of the plurality of memory controllers to generate a first allocation of the plurality of memory operations to the memory controllers, and determines that the first allocation is to be stored as a permanent memory allocation based on a first performance metric associated with the first allocation.