Simulated NVDRAM Page Reclamation in Host Bus Adapters
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Solution Overview
Problem
In Host Bus Adapter (HBA) systems, the practical implementation of Non-Volatile Dynamic Random Access Memory (NVDRAM) is hindered by DRAM size limitations and power consumption, making it impractical for large host system application capacities.
Innovation Solution
The system simulates NVDRAM operations by sectioning host memory into pages, using a combination of DRAM and SSD for cache operations, where an HBA driver processes Input/Output requests and reclaims pages from DRAM to SSD based on access rates, employing a most recently used (MRU) page replacement policy to manage data efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical NVDRAM is implemented in HBA, then data persistence is improved, but device size and power consumption increase making it impractical
Solution Approach 1:
The patent creates a simulated NVDRAM environment by copying the functionality of physical NVDRAM through software emulation in the HBA driver. The driver implements page mapping between host memory and HBA cache, simulating persistent memory behavior without requiring physical NVDRAM hardware, thus achieving data persistence characteristics while avoiding the size and power constraints of physical implementation.
Solution Approach 2:
The patent introduces an intermediary layer (the HBA driver with simulated NVDRAM functionality) between the host system and the physical storage devices. This intermediary simulates persistent memory behavior by managing page mappings and data caching, allowing the system to access data with NVDRAM-like performance and persistence characteristics while using standard DRAM and storage devices, thereby avoiding the need for physical NVDRAM in the HBA.
2Quantity of substance
If DRAM size is increased to meet host system application capacity requirements, then storage capacity is improved, but power consumption increases
Solution Approach 1:
The patent segments the storage hierarchy into multiple levels: host memory, HBA DRAM cache, and backend storage devices. By dividing the storage capacity across these segments and using the HBA driver to manage page mappings between them, the system can provide large storage capacity without requiring a single large DRAM device, thus avoiding the high power consumption associated with large DRAM capacities while maintaining fast access to frequently used data.
3Quantity of substance
If page reclamation rate is increased in simulated NVDRAM, then memory availability is improved, but page fault management latency increases
Solution Approach 1:
The patent implements preliminary actions by pre-managing page reclamation based on access patterns detected by the HBA driver. The driver monitors page access rates and proactively reclaims pages that are unlikely to be accessed soon, maintaining a pool of available memory pages before they are needed. This preliminary reclamation reduces the need for urgent page faults and minimizes latency when memory is required.
Solution Approach 2:
The patent implements feedback mechanisms where the HBA driver continuously monitors page access patterns and adjusts reclamation rates dynamically. By observing which pages are accessed frequently and which are not, the driver can make informed decisions about which pages to reclaim, balancing memory availability with minimal disruption to active pages. This feedback-based approach prevents excessive page faults and maintains low latency while ensuring sufficient memory availability.
Data Source
AI summary
Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD. The DRAM and the SSD are also sectioned into pages and mapped to pages of the host memory. A host processor is operable to generate Input/Output (I/O) requests. An HBA driver is operable to process the I/O requests. The HBA driver is also operable to detect when the pages of the DRAM are accessed, to determine a rate of page reclamation based on the detection, and to reclaim pages of data in the DRAM by moving pages of data from the DRAM into the pages of the SSD based on the determined rate of page reclamation.