Simulating Vector Execution Without Compiler Support
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Solution Overview
Problem
Current simulation tools face challenges in efficiently simulating new instructions without compiler support, leading to unforeseen side effects like memory bottlenecks and long latencies, especially when introducing wider vector instructions, which can result in costly post-silicon redesigns.
Innovation Solution
A simulator is developed with a functional unit, timing unit, and vectorization unit that allows for the simulation of new instructions by identifying vectorizable regions, serially executing them using M-wide vector instructions, and switching to parallel execution once memory dependencies are confirmed, enabling the simulation of N-wide vector instructions not supported by the compiler.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If new wider vector instructions are added to the ISA without compiler support, then performance of multimedia and scientific applications may be improved, but unforeseen side effects such as memory bottlenecks and long latencies occur
Solution Approach 1:
The simulator performs preliminary analysis of memory dependencies in vectorizable regions before executing vector instructions. By checking memory dependencies in advance (principle of preliminary action), the system can identify potential bottlenecks and latency issues before they manifest in actual hardware, allowing for accurate performance estimation without compiler support.
Solution Approach 2:
The system pre-processes program code to identify vectorizable regions and analyze their memory access patterns before simulation execution. This preliminary analysis enables the simulator to predict performance characteristics and detect potential issues such as memory bottlenecks before the hardware is fabricated.
2Speed
If scalar instructions are translated to P-wide vector instructions, then execution speed is improved, but memory bandwidth bottlenecks are encountered
Solution Approach 1:
The simulator applies vectorization partially by translating only those scalar instructions that can be safely vectorized without causing memory bottlenecks. By selectively vectorizing regions and leaving others as scalar operations, the system achieves speed improvement where possible while avoiding the excessive memory bandwidth requirements that would result from full vectorization.
Solution Approach 2:
The system dynamically adjusts the degree of vectorization based on memory dependency analysis. By changing the parameter of vector instruction width from maximum P-wide to appropriate M-wide instructions based on memory constraints, the simulator optimizes execution speed while managing memory bandwidth requirements.
3Measurement precision
If functional-based simulation is used for all iterations, then accuracy is maintained, but simulation time increases significantly
Solution Approach 1:
The simulation process is segmented into different phases: functional-based simulation is used for initial accuracy-critical regions, while timing-based simulation is used for regions where accuracy has been validated. This segmentation allows the system to maintain measurement precision where needed while reducing overall simulation time by using faster timing-based methods in appropriate contexts.
Solution Approach 2:
The simulator dynamically switches between functional-based and timing-based simulation modes based on the specific region being simulated and its memory dependency characteristics. This dynamic approach maintains accuracy for critical regions while minimizing simulation time for less critical regions.
Data Source
AI summary
A system and method for simulating new instructions without compiler support for the new instructions. A simulator detects a given region in code generated by a compiler. The given region may be a candidate for vectorization or may be a region already vectorized. In response to the detection, the simulator suspends execution of a time-based simulation. The simulator then serially executes the region for at least two iterations using a functional-based simulation and using instructions with operands which correspond to P or less lanes of single-instruction-multiple-data (SIMD) execution. The value P is a maximum number of lanes of SIMD exection supported both by the compiler. The simulator stores checkpoint state during the serial execution. In response to determining no inter-iteration memory dependencies exist, the simulator returns to the time-based simulation and resumes execution using N-wide vector instructions.