Simulation Accelerator Prefetching and Parallel Execution
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Solution Overview
Problem
Modern digital design simulations face performance issues due to high memory access latency, especially when dealing with large datasets that do not fit in cache and lack good locality, leading to inefficient use of resources and prolonged processing times.
Innovation Solution
A simulation acceleration system with dedicated hardware that compiles RTL and testbench codes into levelized and un-levelized blocks, using a simulation accelerator to schedule instructions, manage memory transactions, and implement prefetching mechanisms to reduce memory latency and enhance parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If digital design simulation uses large datasets that do not fit in cache, then the simulation can handle more complex designs, but memory access latency increases significantly
Solution Approach 1:
The system performs preliminary actions by prefetching data and instructions into cache memory before they are actually needed for execution. The simulation accelerator identifies upcoming memory access patterns and proactively loads required data into the instruction cache and data cache, thereby eliminating cache miss penalties during critical execution phases.
Solution Approach 2:
The simulation accelerator is divided into multiple independent processor cores that can execute simulation instructions in parallel. Each core has its own instruction cache and data cache, allowing simultaneous access to different portions of the large dataset without contention. This segmentation enables the system to handle larger datasets by distributing memory access across multiple cache hierarchies.
2Productivity
If the system uses multiple processors for parallel execution, then simulation speed increases, but coordination overhead and memory conflict detection increase
Solution Approach 1:
The simulation accelerator introduces an intermediary transaction management mechanism that mediates between multiple processor cores and the shared memory system. Transactions are packaged with metadata indicating their memory access patterns, and the system uses an intermediary buffer to stage memory operations before execution, reducing direct conflicts between parallel cores.
Solution Approach 2:
The system replaces traditional mechanical memory access coordination with a software-based transactional memory model. Instead of using hardware locks and mutual exclusion mechanisms, the simulation accelerator uses software transactions that can be committed or aborted based on conflict detection, reducing the overhead of inter-core coordination.
3Reliability
If the system implements transactional execution with abort conditions, then parallel execution safety is improved, but execution time increases due to potential aborts and restarts
Solution Approach 1:
The system converts the potential harm of transaction aborts into a benefit by using abort information to optimize future execution. When a transaction aborts due to a conflict, the system learns from this conflict and adjusts its transaction boundaries or scheduling decisions to prevent similar aborts in the future, thereby converting execution failures into optimization opportunities.
Solution Approach 2:
The simulation accelerator implements partial transactional execution where only critical sections of code are executed as transactions, while non-critical sections run without transaction overhead. This selective approach ensures that transactions are used only where necessary for correctness, minimizing the impact of aborts and restarts on overall execution time.
4Productivity
If the system uses dedicated simulation accelerator hardware, then simulation performance improves significantly, but device complexity and cost increase
Solution Approach 1:
The simulation accelerator is designed as a universal platform that can execute multiple different simulation kernels and support various digital design simulation workloads. By implementing a standardized instruction set architecture and common transactional memory interface, the hardware can be reused across different simulation scenarios, justifying the complexity through multi-functionality.
Solution Approach 2:
The system allows dynamic configuration of simulation parameters such as the number of processor cores, cache sizes, and transaction buffer depths. This parameter adjustability enables the hardware to be optimized for specific simulation workloads, achieving high performance without requiring a completely different hardware design for each application.
Data Source
AI summary
A simulation acceleration system is provided. The system includes a simulation accelerator that receives compiled code of a design that includes register transfer level (RTL) components and testbench components. The compiled code includes instructions for simulating behaviors of the design. The simulation accelerator schedules the instructions to be executed by multiple processors based on simulation events occurring at different simulation timesteps. The simulation events are determined according to the executed instructions. The simulation accelerator captures trace data generated by the execution of the scheduled instructions and provides the captured trace data.