Simulation Accelerator Parallel Processing RTL Memory Latency

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Solution Overview

Problem

Software-based simulators for designing and verifying digital circuits face inefficiencies due to memory access latency and inability to realize parallel computing benefits, while hardware emulators suffer from significant compilation efforts and limited diagnostic capabilities.

Innovation Solution

A simulation system comprising a simulation accelerator and processor that minimizes memory latency and exploits parallelism in Register Transfer Levels (RTLs), allowing for efficient execution of compiled RTLs and testbench codes, and sorting instructions into groups for parallel processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Difficulty of detecting and measuring

If software-based simulators are used for designing and verifying digital circuits, then diagnostic capabilities are improved, but memory access latency increases and parallel computing benefits cannot be realized

Engineering Contradiction:

Improvediagnostic capabilitiesVSAvoidmemory access latency

Core Design Contradiction:

Difficulty of detecting and measuringVSLoss of time

Solution Approach 1:

The patent replaces the traditional software-based simulation mechanism (which relies on sequential CPU execution and memory access) with a hardware-based simulation accelerator that directly executes compiled RTL code. This substitution eliminates memory access latency by using dedicated hardware circuits and registers to store and process simulation instructions, while maintaining diagnostic capabilities through built-in observation points and signal routing in the hardware architecture.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Difficulty of detecting and measuring

If software-based simulators are used for designing and verifying digital circuits, then diagnostic capabilities are improved, but parallel computing benefits cannot be realized

Engineering Contradiction:

Improvediagnostic capabilitiesVSAvoidparallel computing capability

Core Design Contradiction:

Difficulty of detecting and measuringVSProductivity

Solution Approach 1:

The patent segments the simulation instructions into multiple parallel execution channels within the hardware accelerator. Each channel can independently execute different portions of the compiled RTL code simultaneously, enabling parallel processing of digital circuit verification tasks. The hardware architecture includes multiple functional units and processing elements that operate in parallel, while diagnostic capabilities are maintained through distributed observation points across all parallel channels.

Inventive Principle:

Principle #1Segmentation

3Loss of time

If hardware emulators are used for simulating digital circuits, then memory access latency is reduced and parallel processing is enabled, but compilation efforts increase significantly

Engineering Contradiction:

Improvememory access latencyVSAvoidcompilation efforts

Core Design Contradiction:

Loss of timeVSEase of manufacture

Solution Approach 1:

The patent performs preliminary compilation of RTL code into a specialized intermediate representation format that is optimized for hardware accelerator execution. This compilation process is performed once before simulation, and the resulting compiled code can be efficiently executed by the hardware accelerator with minimal additional processing. The preliminary action of compiling RTL to the accelerator's native format reduces the burden of repeated compilation while enabling fast hardware-based execution with low memory access latency.

Inventive Principle:

Principle #10Preliminary action

4Productivity

If hardware emulators are used for simulating digital circuits, then parallel processing is enabled, but diagnostic capabilities are limited

Engineering Contradiction:

Improveparallel processing capabilityVSAvoiddiagnostic capabilities

Core Design Contradiction:

ProductivityVSDifficulty of detecting and measuring

Solution Approach 1:

The hardware accelerator is designed with multi-functional capabilities that combine high-speed parallel processing with comprehensive diagnostic features. The system includes built-in observation points, signal routing, and monitoring capabilities that allow engineers to diagnose and analyze circuit behavior while maintaining parallel execution performance. The universal design integrates both computation and diagnostics into a single hardware platform, eliminating the trade-off between parallel processing capability and diagnostic functionality.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11275582B2Event-driven design simulation

Publication Date: 2022.03.15 SIEMENS INDUSTRY SOFTWARE INC

AI summary

A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.