Simulation Checkpointing System for Signal Value Retrieval

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Solution Overview

Problem

Logic simulators face limitations in storing and retrieving signal values due to memory constraints, requiring multiple simulation runs and increasing edit-debug time, as they cannot store all signal values generated during complex simulations, leading to inefficiencies in diagnosing and correcting design errors.

Innovation Solution

The implementation of a checkpointing system that includes a runtime array, a checkpoint cache, and a hyper-checkpoint array to store and retrieve signal values, allowing for the retrieval of any signal value and rewinding the simulator to a user-specified time, thereby making all signal values available and reducing the need for full simulation reruns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If memory capacity is increased to store all signal values, then signal value availability is improved, but cost and practicality deteriorate

Engineering Contradiction:
Improvesignal value availabilityVSAvoidmemory capacity
Core Design Contradiction:
Loss of informationVSQuantity of substance

Solution Approach 1:

The memory system is divided into multiple segments: runtime array for current values, checkpoint cache for intermediate values, and checkpoint array for historical values. This segmentation allows comprehensive signal value storage without requiring a single large memory block, making the system more practical while maintaining full signal availability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary checkpointing of signal values at scheduled intervals during simulation. By proactively storing values in the checkpoint cache before they are needed for analysis, the system ensures signal availability without requiring excessive memory capacity during the simulation run.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If entire simulation is rerun to check design corrections, then accuracy is improved, but time consumption deteriorates

Engineering Contradiction:
Improvedesign verification accuracyVSAvoidedit-debug time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary checkpointing of simulation states at intervals. When a design correction is made, the system can restore from a previously checkpointed state and only re-simulate the affected portion of the design, rather than rerunning the entire simulation. This maintains verification accuracy while significantly reducing edit-debug time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system extracts and stores intermediate simulation states in the checkpoint cache. This allows the designer to take out only the necessary simulation data for re-verification after corrections, avoiding the need to re-execute unrelated portions of the simulation and reducing overall time consumption.

Inventive Principle:
Principle #2Taking out (Extraction)

3Measurement precision

If multiple simulation runs are performed to obtain all necessary information, then diagnostic accuracy is improved, but productivity deteriorates

Engineering Contradiction:
Improveerror diagnosis accuracyVSAvoiddesign iteration speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The checkpointing system segments simulation data into manageable units stored in the checkpoint cache and array. This allows the designer to efficiently access specific signal values and time points from multiple simulation runs without manually re-running simulations, thereby maintaining diagnostic accuracy while improving productivity through faster data retrieval and analysis.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8050903B1Apparatus and method for checkpointing simulation data in a simulator
Publication Date: 2011.11.01 TEXAS INSTRUMENTS INC
  • US8050903B1 patent drawing
  • US8050903B1 patent drawing
  • US8050903B1 patent drawing

AI summary

Apparatus for storing all logic simulation signal values generated by a logic simulator during a simulation run is provided. The apparatus includes a runtime array for storing a plurality of signal values for each time instance in a predetermined time period, and a checkpoint cache for selectively storing the plurality of signal values stored in the runtime array at selected time instances. A hyper-checkpoint array is further provided to checkpoint the signal values in the checkpoint cache. In addition, the time instances and values of memory writes are also checkpointed. A user may retrieve the value of any signal values generated during the simulation run and may additionally rewind the simulator to a user-specified time in the simulation run.