Simulation Clock Scheduling for Deterministic Distributed Simulation

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Solution Overview

Problem

Conventional distributed processing systems execute asynchronously, leading to non-deterministic behavior, which complicates simulation testing and problem identification due to variability in node execution sequences and inter-process communication latencies.

Innovation Solution

The system replaces complex multi-threaded nodes with smaller nodelets that can operate in single-threaded or multi-threaded modes, scheduling them to execute serially within defined timeframes and using a simulated clock for deterministic processing, ensuring consistent output across simulations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If distributed processing systems execute asynchronously with multi-threaded nodes, then processing speed and concurrency are improved, but execution determinism and simulation reliability deteriorate due to variability in node execution sequences and inter-process communication latencies

Engineering Contradiction:
Improveprocessing speedVSAvoidexecution determinism
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the distributed processing system into discrete publish events and subscriber events that can be independently scheduled and executed. By dividing the continuous asynchronous execution into discrete time-sliced events, the system maintains high processing throughput while ensuring deterministic execution order within each time slice, resolving the contradiction between processing speed and execution determinism

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements periodic time-sliced execution where the simulated clock advances in discrete periods, and within each period, publish and subscriber events are executed in a deterministic sequence. This periodic structure ensures that while the overall system processes data continuously at high speed, each time slice maintains deterministic behavior, reconciling the need for both processing speed and execution reliability

Inventive Principle:
Principle #19Periodic action

2Adaptability or versatility

If simulated sensor data is processed through distributed subsystems, then system functionality is improved, but simulation variability and testing complexity increase due to non-deterministic execution sequences

Engineering Contradiction:
Improvesystem functionalityVSAvoidsimulation testing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent creates a simulated clock that copies the timing behavior of real system clocks but operates in a controlled, deterministic manner. This simulated clock provides identical timing information to all subsystems during simulation, ensuring that the same input data always produces the same execution sequence and output results, thereby simplifying simulation testing while maintaining full system functionality

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent introduces a simulated clock as an intermediary between the test controller and the distributed subsystems. This intermediary manages the execution timing and sequence of all subsystems, allowing the test controller to initiate simulations without dealing with the complexity of coordinating multiple asynchronous processes, thus reducing testing complexity while preserving system functionality

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11397610B2Architecture for simulation clock-based simulation of distributed systems
Publication Date: 2022.07.26 BEIJING VOYAGER TECH CO LTD
  • US11397610B2 patent drawing
  • US11397610B2 patent drawing
  • US11397610B2 patent drawing

AI summary

Systems and methods are provided for the deterministic simulation of distributed systems, such as vehicle-based processing systems. A distributed system may be represented as a plurality of subsystems or “nodelets” executing with a single process of a computing device during a simulation. The nodelets may communicate using in-process communication. A task scheduler can schedule the nodelets to execute separately in serially-occurring frames. A simulated clock may be used to mitigate the variability in timestamped data that may be caused by latency or jitter.