Simulation Code Merging for HDL Compilation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing HDL simulators generate large amounts of simulation code and require significant memory due to separate code generation for each instance of a process, leading to inefficient runtime performance.
Innovation Solution
The method involves generating simulation code that can model multiple instances of a process with the same hardware configuration, using a first portion of code to simulate the module and a second portion to execute using respective nets corresponding to each instance, reducing code size and improving memory efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate simulation code is generated for each instance of a process, then each instance can be simulated independently, but the size of simulation code and memory requirements increase significantly
Solution Approach 1:
The patent merges simulation code for multiple instances of the same process into a single shared code base. Instead of generating separate code for each instance, the system generates one simulation code that can be reused across all instances, significantly reducing code size and memory requirements while maintaining the ability to simulate multiple instances independently
Solution Approach 2:
The simulation code is designed to be universal and multi-functional, capable of simulating any number of process instances through parameterization. The code uses generic variables and structured data to represent different instances, allowing a single code base to handle multiple instances without requiring instance-specific code generation
2Reliability
If separate simulation code is generated for each process instance, then instance-specific behavior can be accurately modeled, but runtime performance deteriorates due to larger code execution overhead
Solution Approach 1:
By merging simulation code for multiple instances into a single shared code base, the patent reduces the total code volume that must be executed during runtime. This consolidation eliminates redundant code execution overhead while maintaining accurate instance-specific simulation through parameterized variables and structured data representations
Solution Approach 2:
The system uses parameter changes to adapt the universal simulation code to different instances. Instead of generating different code for each instance, the code uses parameterized variables and data structures that can be configured at runtime to represent different instance characteristics, maintaining accuracy while reducing execution overhead
3Reliability
If separate code portions are generated for each process instance, then complete simulation coverage is achieved, but memory requirements increase significantly
Solution Approach 1:
The patent merges the simulation code for all process instances into a single shared code base stored in memory. This consolidation maintains complete simulation coverage through parameterized variables and structured data while dramatically reducing the total memory required to store the simulation code, as the same code is shared across all instances rather than stored separately for each
Data Source
AI summary
In one embodiment, a method for compiling an HDL specification for simulation of a circuit design is provided. Using one or more processors the circuit design is elaborated from the HDL specification. Two or more instances of a module of the elaborated design that have a same hardware configuration are determined. Simulation code that models the circuit design is generated. A first portion of the simulation code is configured to model the module having the hardware configuration. For each of the two or more instances, a second portion of the simulation code is configured to, in response to an indication to simulate the instance, execute the first portion of simulation code using a respective set of nets corresponding to the instance.