Modified Simulation Compiler Emulation Semantics
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Solution Overview
Problem
Current design verification processes for integrated circuits face challenges with slow simulation speeds, long turnaround times, and high costs associated with hardware-based emulation, particularly during early design bring-up and regression testing.
Innovation Solution
A processing device modifies a simulation compiler to match emulation semantics, allowing for design verification using a simulation compiler that has been transformed to perform like an emulation compiler, thereby improving performance and reducing turnaround time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware-based emulation is used for design verification, then verification accuracy and capability are improved, but cost and turnaround time increase
Solution Approach 1:
The patent creates a modified simulation compiler that copies the essential semantics and behavior of the emulation compiler, allowing simulation to replicate emulation-like verification capabilities without the associated cost and time penalties. The modified simulation compiler mimics how the emulation compiler processes RTL code, handles clock generation events, and evaluates expressions, thereby providing accurate verification results through software simulation rather than expensive hardware emulation.
2Reliability
If hardware-based emulation is used for design verification, then verification accuracy is improved, but cost increases
Solution Approach 1:
The patent creates a modified simulation compiler that copies the essential semantics and behavior of the emulation compiler, allowing simulation to replicate emulation-like verification capabilities without the associated cost and time penalties. The modified simulation compiler mimics how the emulation compiler processes RTL code, handles clock generation events, and evaluates expressions, thereby providing accurate verification results through software simulation rather than expensive hardware emulation.
3Productivity
If simulation compiler is used for design verification, then cost and turnaround time are reduced, but verification capability deteriorates
Solution Approach 1:
The patent applies local quality by making the simulation compiler selectively emulate only the specific semantics and behaviors that are critical for accurate verification, rather than attempting to replicate the entire emulation system. The modified simulation compiler focuses on accurately handling clock generation events, expression evaluation, and RTL statement processing - the local aspects that most impact verification capability - while maintaining the speed and efficiency of software simulation.
4Reliability
If simulation compiler is modified to match emulation semantics, then verification capability is improved, but compiler complexity increases
Solution Approach 1:
The patent applies dynamics by making the simulation compiler adaptable and configurable to match emulation semantics only when and where needed. The compiler can dynamically adjust its behavior based on the specific RTL statements being processed, enabling it to emulate emulation-like verification capabilities while maintaining the flexibility to optimize performance and manage complexity through selective application of emulation semantics.
Data Source
AI summary
A processing device receives one or more inputs for design verification of an integrated circuit using an emulation compiler. The processing device determines a type of compiler for processing the one or more inputs. In response to determining that the type of compiler is a simulation compiler, the processing device modifies the simulation compiler according to the one or more inputs to form a modified simulation compiler to match one or more emulation semantics associated with the emulation compiler. The processing device performs a design verification using the modified simulation compiler.