Simulation Coverage Ranking for IC Verification

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Solution Overview

Problem

The complexity of integrated circuit (IC) design verification, particularly in consumer electronics, is hindered by the difficulty in merging and ranking coverage data from multiple simulation runs with varying configurations and abstraction levels, leading to inefficiencies in identifying redundant tests and optimizing the verification process.

Innovation Solution

A computer-implemented method for verifying digital designs that merges and ranks tests based on different configurations, allowing for concurrent system-level and block-level testing, and determining redundant test runs to optimize the verification process by generating a target model and using a rank configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If coverage data from multiple simulation runs with varying configurations are merged, then a comprehensive view of coverage is achieved, but the complexity of merging and ranking increases

Engineering Contradiction:
Improvecomprehensive coverage viewVSAvoidmerging and ranking complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the coverage data by organizing it into hierarchical structures (design hierarchy, abstraction levels) and processes it in manageable portions through staged merging. Different coverage databases from various simulation runs are segmented and then systematically integrated, reducing the overall complexity of handling comprehensive coverage data.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary ranking mechanism that mediates between the raw coverage data from multiple simulation runs and the final comprehensive coverage view. This intermediary process standardizes and ranks coverage items before merging, simplifying the overall process of integrating data from varying configurations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If multiple design teams work on individual blocks with different abstraction levels, then design flexibility and specialization are improved, but the difficulty of stitching coverage results increases

Engineering Contradiction:
Improvedesign flexibilityVSAvoidcoverage stitching complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent creates a universal coverage framework that can handle multiple abstraction levels (system-level, block-level, component-level) within a single integrated system. The coverage stitching mechanism is designed to be multi-functional, accommodating different abstraction levels and design team contributions while maintaining a unified view of coverage across the entire design.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent adds a dimensional layer to coverage management by introducing abstraction level as a new dimension for organizing coverage data. This allows coverage from different abstraction levels to be systematically stitched together by treating them as different dimensions of the same overall coverage space, rather than attempting to flatten them into a single level.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If test ranking is performed to remove redundant tests, then verification efficiency is improved, but the time required for ranking increases

Engineering Contradiction:
Improveverification efficiencyVSAvoidranking time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by pre-processing and pre-ranking coverage data before the final verification process. Coverage items are pre-organized and pre-ranked based on their importance and redundancy characteristics, so that when the actual verification runs, the ranking process is significantly accelerated because the heavy lifting has already been done in advance.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9098637B1Ranking process for simulation-based functional verification
Publication Date: 2015.08.04 CADENCE DESIGN SYST INC
  • US9098637B1 patent drawing
  • US9098637B1 patent drawing
  • US9098637B1 patent drawing

AI summary

The present disclosure relates to a method for verifying a digital design using a computing device. The method may include determining one or more tests associated with verifying the digital design and generating, using the computing device, a verification result by performing one or more verification runs on the digital design. The method may further include merging coverage data generated by the one or more verification runs and ranking the one or more tests based upon, at least in part, a first verification run having a first configuration and a second verification run having a second configuration, wherein the first and second configurations differ.