Automated Simulation Model Partitioning for Processor and FPGA
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Solution Overview
Problem
Existing methods for dividing simulation models between processors and programmable logic modules (FPGAs) require manual identification and shifting of model boundaries, which is time-consuming and inefficient, especially for complex real-time simulations.
Innovation Solution
A method that automatically divides a graphical simulation model into sub-models for execution on processors and FPGAs by identifying blocks based on sampling time and resource allocation, forming cyclic and non-cyclic groups, and allocating them to appropriate domains, generating program code for processors and configuration bitstreams for FPGAs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual identification and shifting of model boundaries is used to divide simulation models between processor and FPGA, then the partitioning can be customized according to specific requirements, but the process is time-consuming and inefficient
Solution Approach 1:
The system automatically divides the simulation model into processor and FPGA sub-models using algorithms that analyze sampling times and resource allocations, eliminating the need for manual boundary identification and shifting while still achieving optimized partitioning
Solution Approach 2:
The automatic division method uses parameters such as sampling times and resource allocations to determine optimal partition boundaries, transforming the manual trial-and-error process into an automated parameter-driven optimization process
2Device complexity
If complex real-time simulations are executed on processor only, then the system is simpler to implement, but the latency requirements cannot be met
Solution Approach 1:
The simulation model is segmented into two parts: sub-models with strict latency requirements are allocated to FPGA for high-speed execution, while other sub-models run on the processor, creating a heterogeneous computing system that meets both latency and complexity requirements
Solution Approach 2:
The system dynamically allocates different sub-models to appropriate execution platforms (processor or FPGA) based on their specific requirements, allowing the system to adaptively meet varying latency demands while maintaining manageable overall complexity
3Reliability
If heterogeneous arithmetic logic units (processor and FPGA) are used for complex real-time simulations, then the latency requirements can be met, but the system complexity increases
Solution Approach 1:
The automatic model division system provides a universal framework that handles both processor and FPGA execution, managing the complexity of heterogeneous computing through automated algorithms that work across different execution platforms without requiring separate manual configuration processes
Data Source
AI summary
A method for dividing a graphical simulation model up into a first sub-model and a second sub-model includes: identifying at least one first block as belonging to the first sub-model and identifying at least one second block as belonging to the second sub-model based on a sampling time and/or a resource allocation; searching for cyclic groups of blocks, wherein a cyclic group whose blocks all have the same sampling time is deemed to be atomic; identifying non-cyclic groups of blocks; allocating individual blocks from the cyclic groups of blocks and the non-cyclic group of blocks to either the first sub-model or the second sub-model, wherein all blocks of an atomic cyclic group are allocated to the same sub-model; generating program code for the processor from the first sub-model; and generating a configuration bitstream for the programmable logic module from the second sub-model.