Digital Simulation State Verification via Intermediary Module
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Solution Overview
Problem
The simulation of digital hardware devices using four-value logic systems, particularly with X (unknown) values, can lead to errors due to uncertainty in how physical hardware behaves, making it difficult to verify deterministic starting states without modifying the source code.
Innovation Solution
A system and method that create an instance of a first module within a target module to reset and verify the digital state component, allowing the digital simulation to set the state to a fixed or unknown state without modifying the source code, and compare the updated value to a desired value, generating alerts for mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If X values are used in digital simulation to represent unknown states, then the simulation can handle uncertainty in hardware behavior, but errors occur due to X value propagation through digital logic
Solution Approach 1:
The patent segments the simulation process into distinct phases: deterministic phase (before reset) and non-deterministic phase (after reset). By separating these phases, the system can apply different verification strategies appropriate to each phase, reducing errors from X value propagation while maintaining the ability to represent unknown states.
Solution Approach 2:
The patent applies preliminary action by performing verification of deterministic starting states before the reset operation introduces X values. This allows the system to establish a known good state before uncertainty is introduced, enabling better error detection and reduced simulation errors.
2Measurement precision
If source code modification is performed to verify starting states, then verification capability is improved, but the complexity of the verification process increases
Solution Approach 1:
The patent introduces an intermediary verification module that operates on the simulation output without requiring source code modification. This mediator captures and verifies starting states automatically, improving verification capability while avoiding the complexity of source code changes.
Solution Approach 2:
The patent creates a copy of the starting state information through simulation output capture rather than modifying the original source code. This copying approach enables verification while maintaining the simplicity of the original design and avoiding the complexity of code modifications.
3Manufacturing precision
If reset operation is performed to set digital state component to fixed state, then deterministic verification is enabled, but the simulation cannot predict actual silicon behavior
Solution Approach 1:
The patent performs preliminary verification of the deterministic starting state immediately after reset but before any operations that would introduce hardware-specific behavior variations. This timing allows accurate state verification while the system is still in a controlled, predictable state.
Solution Approach 2:
The patent segments the simulation into phases where deterministic verification occurs in the controlled post-reset phase, while hardware behavior prediction is handled separately in subsequent operational phases. This segmentation allows each phase to be optimized for its specific purpose without compromise.
Data Source
AI summary
A system configured to perform a digital simulation of a hardware device, where the hardware device has a digital state component. The system creates an instance of a first module inside a target module associated with the state component, where the source code of the target module remains unmodified by the instance. The system then resets the simulation, such that the state component is set to one of a fixed state and an unknown state, where the unknown state indicates the digital simulation cannot predict how silicon on the hardware device will behave. The system reads an updated value of the digital state component via the instance of the first module, compares the updated value of the digital state component to a desired value of the digital state component, and generates an alert that the updated value does not match the desired value according to the comparison.